2017-08-31  Olivier Hainque  <hainque@adacore.com>

       gcc/
       * config.gcc (powerpc-wrs-vxworks|vxworksae|vxworksmils): Now
	match as powerpc-wrs-vxworks*.

       libgcc/
       * config.host: Likewise.

From-SVN: r251573

	PR c++/82039
	* include/ext/new_allocator.h (__gnu_cxx::new_allocator::allocate):
	Adjust null pointer constant to avoid warning.

From-SVN: r251570

The MLA by-element instructions have the same restriction as other by-element
instructions whereby the forms operating on vectors of 16-bit integer data
may only use registers v0-v15. We have an iterator for that, applied to the
other patterns generating this instruction, so use that.

gcc/

	* config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>): Fix
	register constraint for by-element operand.
	(aarch64_mls_elt_merge<mode>): Likewise.

From-SVN: r251568

	* pt.c (enclosing_instantiation_of, lambda_fn_in_template_p)
	(regenerated_lambda_fn_p): New.
	(tsubst_decl) [VAR_DECL]: Use enclosing_instantiation_of.
	(tsubst_copy) [VAR_DECL]: Likewise.

From-SVN: r251567

Short branches cannot be used to jump between hot/cold
sections. Update the hook.

gcc/
2017-04-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_can_follow_jump): Check for short
	branches.

From-SVN: r251566

gcc/
2017-04-24  Claudiu Zissulescu  <claziss@synopsys.com>

	* config.gcc: Use g.opt for arc.
	* config/arc/arc.c (LEGITIMATE_SCALED_ADDRESS_P): Deleted,
	functionality moved to ...
	(legitimate_scaled_address_p): New function, ...here.
	(LEGITIMATE_SMALL_DATA_OFFSET_P): New define.
	(LEGITIMATE_SMALL_DATA_ADDRESS_P): Use the above define.
	(legitimate_offset_address_p): Delete TARGET_NO_SDATA_SET
	condition.
	(arc_override_options): Handle G option.
	(arc_output_pic_addr_const): Correct function definition.
	(arc_legitimate_address_p): Use legitimate_scaled_address_p.
	(arc_decl_anon_ns_mem_p): Delete.
	(arc_in_small_data_p): Overhaul this function to take into
	consideration the value given via G option.
	(arc_rewrite_small_data_1): Renamed and corrected old
	arc_rewrite_small_data function.
	(arc_rewrite_small_data): New function.
	(small_data_pattern): Don't use pic_offset_table_rtx.
	* config/arc/arc.h (CC1_SPEC): Recognize G option.
	* config/arc/simdext.md (movmisalignv2hi): Use
	prepare_move_operands function.
	(mov*): Likewise.
	(movmisalign*): Likewise.

gcc/testsuite/
2017-04-24  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/sdata-5.c: New test.
	* gcc.target/arc/arc700-stld-hazard.c: Update test options.

Fix test

From-SVN: r251564

Add alignment check for short load/store instructions used for sdata,
as they request 32-bit aligned short immediate.  Use sdata symbol
alignment information and emit scalled loads/stores whenever is
possible. The scalled address will extend the access range for sdata
symbols.  Allow 64-bit datum into small data section, if double
load/store instructions are present.

gcc/
2017-04-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc-protos.h (compact_sda_memory_operand): Update
	prototype.
	* config/arc/arc.c (arc_print_operand): Output scalled address for
	sdata whenever is possible.
	(arc_in_small_data_p): Allow sdata for 64bit datum when double
	load/stores are available.
	(compact_sda_memory_operand): Check for the alignment required by
	code density instructions.
	* config/arc/arc.md (movsi_insn): Use newly introduced Us0
	constraint.
	* config/arc/constraints.md (Usd): Update constraint.
	(Us0): New constraint.
	(Usc): Update constraint.

gcc/testsuite/
2017-04-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/sdata-3.c: New file.

From-SVN: r251562

2017-08-31  Richard Biener  <rguenther@suse.de>

	PR lto/81968
	* simple-object-elf.c (simple_object_elf_copy_lto_debug_section):
	Keep names of removed global symbols.

From-SVN: r251560

2017-08-31  Richard Biener  <rguenther@suse.de>

	PR middle-end/82054
	* dwarf2out.c (dwarf2out_early_global_decl): Process each
	function only once.

	* g++.dg/gomp/pr82054.C: New testcase.

From-SVN: r251559

2017-08-31  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins):
	Resize type_signature.

From-SVN: r251558

Previously we allowed subregs of non-GPR modes to be base and index
registers in non-strict mode.  In practice such subregs will always
require a reload, so we get better code by disallowing them.

2017-08-31  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_base_register_rtx_p): Only allow
	subregs whose inner modes can be stored in GPRs.
	(aarch64_classify_index): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251557

The comparison results provided by the V_cmp_result/v_cmp_result
attribute were simply the corresponding integer vector.  We'd also
like to have easy access to the integer vector for SVE, but using
"cmp_result" would be confusing because SVE comparisons return
predicates instead of vectors.  This patch therefore renames the
attributes to the more general V_INT_EQUIV/v_int_equiv instead.

As to the capitalisation: there are already many iterators that use
all lowercase vs. all uppercase names to distinguish all lowercase
vs. all uppercase expansions (e.g. fcvt_target and FCVT_TARGET).
It's also the convention used for the built-in mode/MODE/code/CODE/etc.
attributes.  IMO those names are easier to read at a glance, rather than
relying on a single letter's difference.

2017-08-22  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/iterators.md (V_cmp_result): Rename to...
	(V_INT_EQUIV): ...this.
	(v_cmp_result): Rename to...
	(v_int_equiv): ...this.
	* config/aarch64/aarch64.md (xorsign<mode>3): Update accordingly.
	* config/aarch64/aarch64-simd.md (xorsign<mode>3): Likewise.
	(copysign<mode>3): Likewise.
	(aarch64_simd_bsl<mode>_internal): Likewise.
	(aarch64_simd_bsl<mode>): Likewise.
	(vec_cmp<mode><mode>): Likewise.
	(vcond<mode><mode>): Likewise.
	(vcond<v_cmp_mixed><mode>): Likewise.
	(vcondu<mode><v_cmp_mixed>): Likewise.
	(aarch64_cm<optab><mode>): Likewise.
	(aarch64_cmtst<mode>): Likewise.
	(aarch64_fac<optab><mode>): Likewise.
	(vec_perm_const<mode>): Likewise.
	(vcond_mask_<mode><v_cmp_result>): Rename to...
	(vcond_mask_<mode><v_int_equiv>): ...this.
	(vec_cmp<mode><v_cmp_result>): Rename to...
	(vec_cmp<mode><v_int_equiv>): ...this.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251556

The AArch64 port defined x2, x3 and x4 vector modes that were only used
in the rtl for the AdvSIMD LD{2,3,4} patterns.  It seems unlikely that
this rtl would have led to any valid simplifications, since the values
involved were unspecs that had a different number of operands from the
non-dreg versions.  (The dreg UNSPEC_LD2 had a single operand, while
the qreg one had two operands.)

As it happened, the patterns led to invalid simplifications on big-
endian targets due to a mix-up in the operand order, see Tamar's fix
in r240271.

This patch therefore replaces the rtl patterns with dedicated unspecs.
This allows the x2, x3 and x4 modes to be removed, avoiding a clash
with 256-bit and 512-bit SVE.

2017-08-22  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-modes.def: Remove 32-, 48- and 64-byte
	vector modes.
	* config/aarch64/iterators.md (VRL2, VRL3, VRL4): Delete.
	* config/aarch64/aarch64.md (UNSPEC_LD2_DREG, UNSPEC_LD3_DREG)
	(UNSPEC_LD4_DREG): New unspecs.
	* config/aarch64/aarch64-simd.md (aarch64_ld2<mode>_dreg_le)
	(aarch64_ld2<mode>_dreg_be): Replace with...
	(aarch64_ld2<mode>_dreg): ...this pattern and use the new DREG
	unspec.
	(aarch64_ld3<mode>_dreg_le)
	(aarch64_ld3<mode>_dreg_be): Replace with...
	(aarch64_ld3<mode>_dreg): ...this pattern and use the new DREG
	unspec.
	(aarch64_ld4<mode>_dreg_le)
	(aarch64_ld4<mode>_dreg_be): Replace with...
	(aarch64_ld4<mode>_dreg): ...this pattern and use the new DREG
	unspec.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251555

strcpy will keep reading and writing memory if the string is not terminated
with null character. In this case, it may visit memory beyond the boundary.

gcc/testsuite/

2017-08-31  Renlin Li  <renlin.li@arm.com>
	    Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

	* gcc.dg/memcmp-1.c (test_strncmp): Use memcpy instead of strcpy.


Co-Authored-By: Aaron Sawdey <acsawdey@linux.vnet.ibm.com>

From-SVN: r251554

From-SVN: r251553

	PR c++/80767
	* call.c (compare_ics): Handle null candidate.

From-SVN: r251549

cp/

* pt.c (unify_overload_resolution_failure): Remove.
(unify_one_argument): Adjust.

testsuite/

* g++.dg/overload/template6.C: New.

From-SVN: r251548

[gcc]

2017-08-30  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR tree-optimization/81987
	* gimple-ssa-strength-reduction.c (insert_initializers): Don't
	insert an initializer in a location not dominated by the stride
	definition.

[gcc/testsuite]

2017-08-30  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR tree-optimization/81987
	* g++.dg/torture/pr81987.C: New file.

From-SVN: r251547

tree-eh.c (lower_try_finally_switch): Set the location of the finally on the entire header of the finally block in...

	* tree-eh.c (lower_try_finally_switch): Set the location of the finally
	on the entire header of the finally block in the fallthru case.

From-SVN: r251546

From-SVN: r251545

rs6000.c (rs6000_emit_prologue_move_from_cr): Rename from rs6000_emit_move_from_cr and call renamed function.

	* config/rs6000/rs6000.c (rs6000_emit_prologue_move_from_cr): Rename from
	rs6000_emit_move_from_cr and call renamed function.
	(rs6000_emit_prologue): Call renamed functions.
	* config/rs6000/rs6000.md (prologue_movesi_from_cr): Rename from
	movesi_from_cr, remove volatile CRs.

	* gcc.target/powerpc/cr_shrink-wrap.c: New.

From-SVN: r251543

From-SVN: r251541

	* configure.ac: Substitute GOC_FOR_TARGET and GCC_FOR_TARGET.
	* Makefile.am (MOSTLYCLEANFILES): Add check-gcc.
	(check-gccgo): Create via a temporary file.
	(check-gcc): New target.
	(CHECK_ENV): Set CC.
	(ECHO_ENV): Report CC.
	(check-go-tool): Depend on check-gcc.
	(check-runtime, check-cgo-test, check-carchive-test): Likewise.
	* configure, Makefile.in: Rebuild.

From-SVN: r251540

re PR target/82015 (PowerPC should check if 2nd argument to __builtin_unpackv1ti and similar functions is 0 or 1)

2017-08-30  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/82015
	* gcc.target/powerpc/pr82015.c: Fix up error message.

From-SVN: r251539

	* tree-vect-patterns.c (vect_pattern_recog_1): Use VECTOR_TYPE_P instead
	of VECTOR_MODE_P check.
	* tree-vect-stmts.c (get_vectype_for_scalar_type_and_size): Allow single
	element vector types.


Co-Authored-By: Richard Biener <rguenther@suse.de>

From-SVN: r251538

...it's really a general RTL predicate, rather than something that depends
on the DF state.  Thanks to Segher for the suggestion.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* df.h (df_read_modify_subreg_p): Remove in favor of...
	* rtl.h (read_modify_subreg_p): ...this new function.  Take a
	const_rtx instead of an rtx.
	* cprop.c (local_cprop_find_used_regs): Update accordingly.
	* df-problems.c (df_word_lr_mark_ref): Likewise.
	* ira-lives.c (mark_pseudo_reg_live): Likewise.
	(mark_pseudo_reg_dead): Likewise.
	(mark_ref_dead): Likewise.
	* reginfo.c (init_subregs_of_mode): Likewise.
	* sched-deps.c (sched_analyze_1): Likewise.
	* df-scan.c (df_def_record_1): Likewise.
	(df_uses_record): Likewise.
	(df_read_modify_subreg_p): Remove in favor of...
	* rtlanal.c (read_modify_subreg_p): ...this new function.  Take a
	const_rtx instead of an rtx.

From-SVN: r251537

This patch adds a partial_subreg_p predicate to go alongside
paradoxical_subreg_p.

Like the paradoxical_subreg_p patch, this one replaces some tests that
were based on GET_MODE_SIZE rather than GET_MODE_PRECISION.  In each
case the change should be a no-op or an improvement.

The regcprop.c patch prevents some replacements of the 82-bit RFmode
with the 80-bit XFmode on ia64.  I don't understand the target details
here particularly well, but from the way the modes are described in
ia64-modes.def, it isn't valid to assume that an XFmode can carry an
RFmode payload.  A comparison of the testsuite assembly output for one
target per CPU showed no other differences.

Some of the places changed here are tracking the widest access mode
found for a register.  The series tries to standardise on:

  if (partial_subreg_p (widest_seen, new_mode))
    widest_seen = new_mode;

rather than:

  if (paradoxical_subreg_p (new_mode, widest_seen))
    widest_seen = new_mode;

Either would have been OK.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* rtl.h (partial_subreg_p): New function.
	* caller-save.c (save_call_clobbered_regs): Use it.
	* calls.c (expand_call): Likewise.
	* combine.c (combinable_i3pat): Likewise.
	(simplify_set): Likewise.
	(make_extraction): Likewise.
	(make_compound_operation_int): Likewise.
	(gen_lowpart_or_truncate): Likewise.
	(force_to_mode): Likewise.
	(make_field_assignment): Likewise.
	(reg_truncated_to_mode): Likewise.
	(record_truncated_value): Likewise.
	(move_deaths): Likewise.
	* cse.c (record_jump_cond): Likewise.
	(cse_insn): Likewise.
	* cselib.c (cselib_lookup_1): Likewise.
	* expmed.c (extract_bit_field_using_extv): Likewise.
	* function.c (assign_parm_setup_reg): Likewise.
	* ifcvt.c (noce_convert_multiple_sets): Likewise.
	* ira-build.c (create_insn_allocnos): Likewise.
	* lra-coalesce.c (merge_pseudos): Likewise.
	* lra-constraints.c (match_reload): Likewise.
	(simplify_operand_subreg): Likewise.
	(curr_insn_transform): Likewise.
	* lra-lives.c (process_bb_lives): Likewise.
	* lra.c (new_insn_reg): Likewise.
	(lra_substitute_pseudo): Likewise.
	* regcprop.c (mode_change_ok): Likewise.
	(maybe_mode_change): Likewise.
	(copyprop_hardreg_forward_1): Likewise.
	* reload.c (push_reload): Likewise.
	(find_reloads): Likewise.
	(find_reloads_subreg_address): Likewise.
	* reload1.c (alter_reg): Likewise.
	(eliminate_regs_1): Likewise.
	* simplify-rtx.c (simplify_unary_operation_1): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251536

        * config/rs6000/rs6000.c (rs6000_expand_binop_builtin): Revert
        back to if statements, including unpack.

From-SVN: r251535

	* simple-object-xcoff.c (simple_object_xcoff_find_sections):
	Improve .go_export csect handling.  Don't make assumptions
	on containing section or number of auxiliary entries.

From-SVN: r251533

2017-08-30  Martin Liska  <mliska@suse.cz>

	PR inline-asm/82001
	* ipa-icf-gimple.c (func_checker::compare_tree_list_operand):
	Rename to ...
	(func_checker::compare_asm_inputs_outputs): ... this function.
	(func_checker::compare_gimple_asm): Use the function to compare
	also ASM constrains.
	* ipa-icf-gimple.h: Rename the function.
2017-08-30  Martin Liska  <mliska@suse.cz>

	PR inline-asm/82001
	* gcc.dg/ipa/pr82001.c: New test.

From-SVN: r251530

From-SVN: r251529

This patch adds another machine_mode wrapper for modes that are
known to be COMPLEX_MODE_P.  There aren't yet many places that make
use of it, but that might change in future.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* coretypes.h (complex_mode): New type.
	* gdbhooks.py (build_pretty_printer): Handle it.
	* machmode.h (complex_mode): New class.
	(complex_mode::includes_p): New function.
	(is_complex_int_mode): Likewise.
	(is_complex_float_mode): Likewise.
	* genmodes.c (get_mode_class): Handle complex mode classes.
	* function.c (expand_function_end): Use is_complex_int_mode.

gcc/go/
	* go-lang.c (go_langhook_type_for_mode): Use is_complex_float_mode.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251527

This patch adds a scalar_mode_pod class and uses it to
replace the machine_mode in fixed_value.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* coretypes.h (scalar_mode_pod): New typedef.
	* gdbhooks.py (build_pretty_printer): Handle it.
	* machmode.h (gt_ggc_mx, gt_pch_nx): New functions.
	* fixed-value.h (fixed_value::mode): Change type to scalar_mode_pod.
	* fold-const.c (fold_convert_const_int_from_fixed): Use scalar_mode.
	* tree-streamer-in.c (unpack_ts_fixed_cst_value_fields): Use
	as_a <scalar_mode>.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251526

This patch uses scalar_mode in a few miscellaneous places:

- Previous patches mean mode_to_vector can take a scalar_mode without
  further changes.

- Implicit promotion is limited to scalar types (affects promote_mode
  and sdbout_parms)

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* machmode.h (mode_for_vector): Take a scalar_mode instead
	of a machine_mode.
	* stor-layout.c (mode_for_vector): Likewise.
	* explow.c (promote_mode): Use as_a <scalar_mode>.
	* sdbout.c (sdbout_parms): Use is_a <scalar_mode>.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251525

This patch makes the preferred_simd_mode target hook take a scalar_mode
rather than a machine_mode.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* target.def (preferred_simd_mode): Take a scalar_mode
	instead of a machine_mode.
	* targhooks.h (default_preferred_simd_mode): Likewise.
	* targhooks.c (default_preferred_simd_mode): Likewise.
	* config/arc/arc.c (arc_preferred_simd_mode): Likewise.
	* config/arm/arm.c (arm_preferred_simd_mode): Likewise.
	* config/c6x/c6x.c (c6x_preferred_simd_mode): Likewise.
	* config/epiphany/epiphany.c (epiphany_preferred_simd_mode): Likewise.
	* config/i386/i386.c (ix86_preferred_simd_mode): Likewise.
	* config/mips/mips.c (mips_preferred_simd_mode): Likewise.
	* config/nvptx/nvptx.c (nvptx_preferred_simd_mode): Likewise.
	* config/powerpcspe/powerpcspe.c (rs6000_preferred_simd_mode):
	Likewise.
	* config/rs6000/rs6000.c (rs6000_preferred_simd_mode): Likewise.
	* config/s390/s390.c (s390_preferred_simd_mode): Likewise.
	* config/sparc/sparc.c (sparc_preferred_simd_mode): Likewise.
	* config/aarch64/aarch64.c (aarch64_preferred_simd_mode): Likewise.
	(aarch64_simd_scalar_immediate_valid_for_move): Update accordingly.
	* doc/tm.texi: Regenerate.
	* optabs-query.c (can_vec_mask_load_store_p): Return false for
	non-scalar modes.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251524

This patch makes the scalar_mode_supported_p target hook take a
scalar_mode rather than a machine_mode.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* target.def (scalar_mode_supported_p): Take a scalar_mode
	instead of a machine_mode.
	* targhooks.h (default_scalar_mode_supported_p): Likewise.
	* targhooks.c (default_scalar_mode_supported_p): Likewise.
	* config/aarch64/aarch64.c (aarch64_scalar_mode_supported_p): Likewise.
	* config/alpha/alpha.c (alpha_scalar_mode_supported_p): Likewise.
	* config/arm/arm.c (arm_scalar_mode_supported_p): Likewise.
	* config/avr/avr.c (avr_scalar_mode_supported_p): Likewise.
	* config/c6x/c6x.c (c6x_scalar_mode_supported_p): Likewise.
	* config/i386/i386.c (ix86_scalar_mode_supported_p): Likewise.
	* config/ia64/ia64.c (ia64_scalar_mode_supported_p): Likewise.
	* config/mips/mips.c (mips_scalar_mode_supported_p): Likewise.
	* config/msp430/msp430.c (msp430_scalar_mode_supported_p): Likewise.
	* config/pa/pa.c (pa_scalar_mode_supported_p): Likewise.
	* config/pdp11/pdp11.c (pdp11_scalar_mode_supported_p): Likewise.
	* config/powerpcspe/powerpcspe.c (rs6000_scalar_mode_supported_p):
	Likewise.
	* config/rs6000/rs6000.c (rs6000_scalar_mode_supported_p): Likewise.
	* config/s390/s390.c (s390_scalar_mode_supported_p): Likewise.
	* config/spu/spu.c (spu_scalar_mode_supported_p): Likewise.
	* config/tilegx/tilegx.c (tilegx_scalar_mode_supported_p): Likewise.
	* config/tilepro/tilepro.c (tilepro_scalar_mode_supported_p):
	Likewise.
	* doc/tm.texi: Regenerate.

gcc/c-family/
	* c-attribs.c (vector_mode_valid_p) Fold GET_MODE_INNER call
	into scalar_mode_supported_p call.
	(handle_mode_attribute): Update call to scalar_mode_supported_p.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251523

This patch uses opt_scalar_mode when iterating over scalar modes.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* coretypes.h (opt_scalar_mode): New typedef.
	* gdbhooks.py (build_pretty_printers): Handle it.
	* machmode.h (mode_iterator::get_2xwider): Add overload for
	opt_mode<T>.
	* emit-rtl.c (init_emit_once): Use opt_scalar_mode when iterating
	over scalar modes.
	* expr.c (convert_mode_scalar): Likewise.
	* omp-low.c (omp_clause_aligned_alignment): Likewise.
	* optabs.c (expand_float): Likewise.
	(expand_fix): Likewise.
	* tree-vect-stmts.c (vectorizable_conversion): Likewise.

gcc/c-family/
	* c-common.c (c_common_fixed_point_type_for_size): Use opt_scalar_mode
	for the mode iterator.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251522

The expand_float code:

  /* Unsigned integer, and no way to convert directly.  Convert as signed,
     then unconditionally adjust the result.  */

and the expand_fix code:

  /* For an unsigned conversion, there is one more way to do it.
     If we have a signed conversion, we generate code that compares
     the real value to the largest representable positive number.  If if
     is smaller, the conversion is done normally.  Otherwise, subtract
     one plus the highest signed number, convert, and add it back.

are restricted to scalars, since the expansion branches on a
comparison of the value.  This patch makes that explicit.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* optabs.c (expand_float): Explicitly check for scalars before
	using a branching expansion.
	(expand_fix): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251521

This patch splits the final scalar-only part of convert_mode out
into its own subroutine and treats the modes as scalar_modes there.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* expr.c (convert_mode): Split scalar handling out into...
	(convert_mode_scalar): ...this new function.  Treat the modes
	as scalar_modes.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251520

This patch uses scalar_mode for code that operates only on MODE_INT
and MODE_FLOAT.

2017-08-30  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* omp-expand.c (expand_omp_atomic): Use is_int_mode, is_float_mode
	and scalar_mode.
	* tree-vect-stmts.c (get_vectype_for_scalar_type_and_size): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251519