2007-07-25  Richard Guenther  <rguenther@suse.de>

        * treetree.c (tree_code_generate_return): RETURN_EXPRs
        have volatile type.

From-SVN: r126912

    gcc/
    * Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi.
    * config.gcc (arm*-*-*): Add arm_neon.h to extra headers.
    (with_fpu): Allow --with-fpu=neon.
    * config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
    * config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
    * config/arm/arm-modes.def (EI, OI, CI, XI): New modes.
    * config/arm/arm-protos.h (neon_immediate_valid_for_move)
    (neon_immediate_valid_for_logic, neon_output_logic_immediate)
    (neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret)
    (neon_emit_pair_result_insn, neon_disambiguate_copy)
    (neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad)
    (output_move_neon): Add prototypes.
    * config/arm/arm.c (FL_NEON): New flag for NEON processor capability.
    (all_fpus): Add FPUTYPE_NEON.
    (fp_model_for_fpu): Add NEON field.
    (arm_return_in_memory): Return vectors <= 16 bytes in ARM registers.
    (arm_arg_partial_bytes): Allow NEON vectors to be passed partially
    in registers.
    (arm_legitimate_address_p): Don't support fancy addressing for NEON
    structure moves.
    (thumb2_legitimate_address_p): Likewise.
    (neon_valid_immediate): Recognize and prepare constants suitable for
    NEON instructions.
    (neon_immediate_valid_for_move): New function. Recognize and prepare
    immediates for NEON move instructions.
    (neon_immediate_valid_for_logic): New function. Recognize and
    prepare immediates for NEON logic instructions.
    (neon_output_logic_immediate): New function. Create asm string
    suitable for outputting immediate logic instructions.
    (neon_pairwise_reduce): New function. Implement reduction using
    pairwise operations.
    (neon_expand_vector_init): New function. Expand a (possibly
    non-constant) vector initialization.
    (neon_vector_mem_operand): New function. Memory operands supported
    for quad-word loads/stores to/from ARM or NEON registers. Don't
    allow base+offset addressing for core regs.
    (neon_struct_mem_operand): New function. Valid mems for NEON
    structure moves.
    (coproc_secondary_reload_class): Enable NEON registers to be loaded
    from neon_vector_mem_operand addresses without a secondary register.
    (add_minipool_forward_ref): Handle >8-byte minipool entries.
    (add_minipool_backward_ref): Likewise.
    (dump_minipool): Likewise.
    (push_minipool_fix): Likewise.
    (output_move_quad): New function. Output quad-word moves, loads and
    stores using ARM registers.
    (output_move_vfp): Add support for vectors in VFP (NEON) D
    registers.
    (output_move_neon): Output a NEON load/store to/from a quadword
    register.
    (arm_print_operand): Implement new codes:
    - 'c' for unadorned integers (without a # sign).
    - 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian
    mode.
    - 'e', 'f' for the low and high D parts of a NEON Q register.
    - 'q' outputs a NEON Q register.
    - 'h' outputs ranges of D registers for VLDM/VSTM etc.
    - 'T' prints NEON opcode features from a coded bitmask.
    - 'F' is similar to T, but signed/unsigned codes both print as
    'i'.
    - 't' is similar to T, but 'u' is printed instead of 'p'.
    - 'O' prints 'r' if NEON instruction should perform rounding (as
    specified by bitmask), else prints nothing.
    - '#' is a punctuation character to stop operand numbers from
    running together with following digits in the assembler
    strings for instructions (when using mode attributes).
    (arm_assemble_integer): Handle extra NEON vector modes. Permute
    constant vectors in big-endian mode, where necessary.
    (arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers.
    Handle EI, OI, CI, XI modes.
    (ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3)
    (ashrv2si3): Rename IWMMXT2_BUILTINs to...
    (ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt)
    (lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names.
    (neon_builtin_type_bits): Add enumeration, one bit for each vector
    type.
    (v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP)
    (v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros
    to turn v8qi, etc. into bits defined above.
    (neon_itype): New enumeration. Classifications of NEON builtins.
    (neon_builtin_datum): Define struct. Contains information about
    a single builtin (with multiple modes).
    (CF): Define helper macro for...
    (VAR1...VAR10): Define builtins with a type, name and 1-10 different
    modes.
    (neon_builtin_data): New array. Define information about builtins
    for use during initialization/expansion.
    (arm_init_neon_builtins): New function.
    (arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is
    true.
    (neon_builtin_compare): New function.
    (locate_neon_builtin_icode): New function. Find an insn code for a
    builtin given a function code for that builtin. Also return type of
    builtin (NEON_BINOP, NEON_UNOP etc.).
    (builtin_arg): New enumeration. Types of arguments for builtins.
    (arm_expand_neon_args): New function. Expand a generic NEON builtin.
    Takes a variable argument list of builtin_arg types, terminated by
    NEON_ARG_STOP.
    (arm_expand_neon_builtin): New function. Expand a NEON builtin.
    (neon_reinterpret): New function. Expand NEON reinterpret intrinsic.
    (neon_emit_pair_result_insn): New function. Support returning pairs
    of vectors via a pointer.
    (neon_disambiguate_copy): New function. Set up operands for a
    multi-word copy such that registers do not get clobbered.
    (arm_expand_builtin): Call arm_expand_neon_builtin if fcode >=
    ARM_BUILTIN_NEON_BASE.
    (arm_file_start): Set float-abi attribute for NEON.
    (arm_vector_mode_supported_p): Enable NEON vector modes.
    (arm_mangle_map_entry): New.
    (arm_mangle_map): New.
    (arm_mangle_vector_type): New.
    * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__
    when appropriate.
    (TARGET_NEON): New macro. Target supports NEON.
    (fputype): Add FPUTYPE_NEON.
    (UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used
    for vectorization based on command-line arg.
    (NEON_REGNO_OK_FOR_NREGS): Define.
    (VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE)
    (VALID_NEON_STRUCT_MODE): Define.
    (PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation.
    (arm_builtins): Add ARM_BUILTIN_NEON_BASE.
    * config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec.
    (consttable_16): Add pattern for outputting 16-byte minipool
    entries.
    (movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in
    vec-common.md).
    (vec-common.md, neon.md): Include md files.
    * config/arm/arm.opt (mvectorize-with-neon-quad): Add option.
    * config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define.
    (memory_constraint "Ut", "Un", "Us"): Define.
    * config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros.
    (MMX_char): New mode attribute.
    (addv8qi3, addv4hi3, addv2si3): Remove. Replace with...
    (*add<mode>3_iwmmxt): New insn pattern.
    (subv8qi3, subv4hi3, subv2si3): Remove. Replace with...
    (*sub<mode>3_iwmmxt): New insn pattern.
    (mulv4hi3): Rename to...
    (*mulv4hi3_iwmmxt): This.
    (smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3)
    (umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3)
    (uminv4hi3, uminv2si3): Remove. Replace with...
    (*smax<mode>3_iwmmxt, *umax<mode>3_iwmmxt, *smin<mode>3_iwmmxt)
    (*umin<mode>3_iwmmxt): These.
    (ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with...
    (ashr<mode>3_iwmmxt): This new pattern.
    (lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with...
    (lshr<mode>3_iwmmxt): This new pattern.
    (ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with...
    (ashl<mode>3_iwmmxt): This new pattern.
    * config/arm/neon-docgen.ml: New file. Generate documentation for
    intrinsics.
    * config/arm/neon-gen.ml: New file. Generate arm_neon.h header.
    * config/arm/arm_neon.h: New (autogenerated).
    * config/arm/neon-testgen.ml: New file. Generate NEON tests
    automatically.
    * config/arm/neon.md: New file. Define NEON instructions.
    * config/arm/neon.ml: New file. Abstract description of NEON
    instructions, used to generate arm_neon.h header, documentation and tests.
    * config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md.
    * vec-common.md: New file. Shared parts for iWMMXt and NEON vector
    support.
    * doc/extend.texi (ARM Built-in Functions): Rename and remove
    extraneous comma.
    (ARM NEON Intrinsics): New subsection.
    * doc/arm-neon-intrinsics.texi: New (autogenerated).

    gcc/testsuite/
    * gcc.dg/vect/vect.exp: Check is-effective-target arm_neon_hw.
    * gcc.dg/vect/tree-vect.h: Check for NEON SIMD support.
    * lib/gcc-dg.exp (cleanup-saved-temps): Fix comment.
    * lib/target-supports.exp (check_effective_target_arm_neon_ok)
    (check_effective_target_arm_neon_hw): New.
    * gcc.target/arm/neon/neon.exp: New file.
    * gcc.target/arm/neon/polytypes.c: New file.
    * gcc.target/arm/neon/v*.c (1870 files): New (autogenerated).


Co-Authored-By: Joseph Myers <joseph@codesourcery.com>
Co-Authored-By: Mark Shinwell <shinwell@codesourcery.com>
Co-Authored-By: Paul Brook <paul@codesourcery.com>

From-SVN: r126911

2007-07-25  Janis Johnson  <janis187@us.ibm.com>

	* gcc.c-torture/unsorted/dump-noaddr.c: Reduce string length for
	  targets where an "int" is less than 32 bits wide.

From-SVN: r126910

2007-07-25  Andreas Krebbel  <krebbel1@de.ibm.com>

	* gcc.dg/20070725-1.c: Testcase for revision 126876 added.

From-SVN: r126909

	* gcc.dg/tree-ssa/predcom-1.c (count_averages): Avoid overflow
	  during addition if an int is only 16 bits wide.
	* gcc.dg/tree-ssa/predcom-2.c (fib): Avoid overflow of 16-bit int.

From-SVN: r126908

	* gcc.dg/torture/pr29584.c: Only run test if pointers have the same
	  size as "long int" and are 32 or 64 bits wide.
	* gcc.dg/torture/pr28814.c: Likewise.

From-SVN: r126907

	* gcc.dg/torture/pr30313.c (struct S): Make sure the bit-field is
	  exactly as wide as an int.

From-SVN: r126906

From-SVN: r126905

struct-layout-1_generate.c (COMPAT_PRLL): Define and use throughout as long long printf format specifier.

	* gcc.dg/compat/struct-layout-1_generate.c (COMPAT_PRLL):
	Define and use throughout as long long printf format specifier.
	* g++.dg/compat/struct-layout-1_generate.c (COMPAT_PRLL):
	Likewise.

From-SVN: r126903

include/
	* ternary.h: Remove.

libiberty/
	* Makefile.in (CFILES): Remove ternary.c.
	(REQUIRED_OFILES): Remove ./ternary.o.
	(INSTALLED_HEADERS): Remove ternary.h.
	(ternary.o): Remove.
	* ternary.c: Remove.

From-SVN: r126902

	* regclass.c (move_table): New type.
	(move_cost, may_move_in_cost, may_move_out_cost): Use it.
	(init_move_cost): Break out from ...
	(init_reg_sets_1): ... here; simplify computation of
	have_regs-of_mode and contains_reg_of_mode.
	(record_reg_classes): Unswitch internal loops.
	(copy_cost): Trigger lazy initialization of move cost
	(record_address_regs): Likewise.

From-SVN: r126901

darwin.c (darwin_override_options): Don't force on flag_var_tracking_uninit when no debug info is requested.

2007-07-24  Daniel Berlin  <dberlin@dberlin.org>

	* config/darwin.c (darwin_override_options): Don't force on
	flag_var_tracking_uninit when no debug info is requested.

From-SVN: r126900

2007-07-24  H.J. Lu  <hongjiu.lu@intel.com>

	*  gcc.dg/dfp/fe-convert-2.c: Unconditionally enable testing
	for converting from 1.0e-96 and 0.00048828125 to _Decimal32.

From-SVN: r126898

From-SVN: r126896

From-SVN: r126892

	* cfgloop.c (init_loops_structure): New function.
	(flow_loops_find): Create root of the loop tree unconditionally.

From-SVN: r126891

	* tree-ssa-ccp.c (fold_const_aggregate_ref): Use fold_convert.

	* gcc.c-torture/execute/20070724-1.c: New.

From-SVN: r126888

2007-07-24 Paul Thomas <pault@gcc.gnu.org>

	PR fortran/31205
	PR fortran/32842
	* trans-expr.c (gfc_conv_function_call): Remove the default
	initialization of intent(out) derived types.
	* symbol.c (gfc_lval_expr_from_sym): New function.
	* matchexp.c (gfc_get_parentheses): Return argument, if it is
	character and posseses a ref.
	* gfortran.h : Add prototype for gfc_lval_expr_from_sym.
	* resolve.c (has_default_initializer): Move higher up in file.
	(resolve_code): On detecting an interface assignment, check
	if the rhs and the lhs are the same symbol.  If this is so,
	enclose the rhs in parenetheses to generate a temporary and
	prevent any possible aliasing.
	(apply_default_init): Remove code making the lval and call
	gfc_lval_expr_from_sym instead.
	(resolve_operator): Give a parentheses expression a type-
	spec if it has no type.
	* trans-decl.c (gfc_trans_deferred_vars): Apply the a default
	initializer, if any, to an intent(out) derived type, using
	gfc_lval_expr_from_sym and gfc_trans_assignment.  Check if
	the dummy is present.


2007-07-24 Paul Thomas <pault@gcc.gnu.org>

	PR fortran/31205
	* gfortran.dg/alloc_comp_basics_1.f90 : Restore number of
	"deallocates" to 24, since patch has code rid of much spurious
	code.
	* gfortran.dg/interface_assignment_1.f90 : New test.

	PR fortran/32842
	* gfortran.dg/interface_assignment_2.f90 : New test.

From-SVN: r126886

2007-07-24 Paul Thomas <pault@gcc.gnu.org>

	PR fortran/31205
	PR fortran/32842
	* trans-expr.c (gfc_conv_function_call): Remove the default
	initialization of intent(out) derived types.
	* symbol.c (gfc_lval_expr_from_sym): New function.
	* matchexp.c (gfc_get_parentheses): Return argument, if it is
	character and posseses a ref.
	* gfortran.h : Add prototype for gfc_lval_expr_from_sym.
	* resolve.c (has_default_initializer): Move higher up in file.
	(resolve_code): On detecting an interface assignment, check
	if the rhs and the lhs are the same symbol.  If this is so,
	enclose the rhs in parenetheses to generate a temporary and
	prevent any possible aliasing.
	(apply_default_init): Remove code making the lval and call
	gfc_lval_expr_from_sym instead.
	(resolve_operator): Give a parentheses expression a type-
	spec if it has no type.
	* trans-decl.c (gfc_trans_deferred_vars): Apply the a default
	initializer, if any, to an intent(out) derived type, using
	gfc_lval_expr_from_sym and gfc_trans_assignment.  Check if
	the dummy is present.


2007-07-24 Paul Thomas <pault@gcc.gnu.org>

	PR fortran/31205
	* gfortran.dg/alloc_comp_basics_1.f90 : Restore number of
	"deallocates" to 24, since patch has code rid of much spurious
	code.
	* gfortran.dg/interface_assignment_1.f90 : New test.

	PR fortran/32842
	* gfortran.dg/interface_assignment_2.f90 : New test.

From-SVN: r126885

	* method.c (implicitly_declare_fn): Increase alignment if member
	function pointer format requires it.

From-SVN: r126884

gcc/fortran:
2007-07-24  Daniel Franke  <franke.daniel@gmail.com>

	PR fortran/32867
	* expr.c (check_init_expr): Simplify matched functions.

gcc/testsuite:
2007-07-24  Daniel Franke  <franke.daniel@gmail.com>

	PR fortran/32867
	* fortran.dg/initialization_10.f90: New test.

From-SVN: r126882

gcc/fortran:
2007-07-24  Daniel Franke  <franke.daniel@gmail.com>

	PR fortran/32778
	* intrinsic.c (add_sym): Do not exclude any symbols, even if not part
	of the selected standard.
	(make generic): Likewise.
	(make alias): Likewise, set standard the alias belongs to.
	(add_subroutines): Call make_noreturn unconditionally.
	(check_intrinsic_standard): Change return value to try.
	(gfc_intrinsic_func_interface): Check return value of above function.
	(gfc_intrinsic_sub_interface): Likewise.

gcc/testsuite:
2007-07-24  Daniel Franke  <franke.daniel@gmail.com>

	PR fortran/32778
	* gfortran.dg/imag_2.f: Removed
	* gfortran.dg/warn_std_1.f90: New test.
	* gfortran.dg/warn_std_2.f90: New test.
	* gfortran.dg/warn_std_3.f90: New test.

From-SVN: r126881

	* caller-save.c: Include ggc.h, gt-caller-save.h
	(reg_save_code, reg_restore_code): Rename to ...
	(cached_reg_save_code, cached_reg_restore_code): ... those.
	(savepat, restpat, test_reg, test_mem, saveinsn, restinsn): New.
	(reg_save_code, reg_restore_code): New functions.
	(init_caller_save): Do not intialize
	reg_save_code/reg_restore_code tables.
	* Makeifle.in: (gt-caller-save.h): New.

From-SVN: r126879

gcc/fortran/
2007-07-24  Tobias Burnus  <burnus@net-b.de>

	* ChangeLog: Correct entry.

libgfortran/
2007-07-24  Tobias Burnus  <burnus@net-b.de>

       * libgfortran.h:  Add bounds_check to compile_options_t.

From-SVN: r126877

tree-ssa-ifcombine.c (ifcombine_ifandif): Use a ONE operand with the mode of the original operand instead of integer_one_node.

2007-07-24  Andreas Krebbel  <krebbel1@de.ibm.com>

	* tree-ssa-ifcombine.c (ifcombine_ifandif): Use a ONE operand
	with the mode of the original operand instead of
	integer_one_node.

From-SVN: r126876

/cp
2007-07-24  Paolo Carlini  <pcarlini@suse.de>

	PR c++/29001
	* typeck.c (check_return_expr): Do not pass a null argument
	to null_ptr_cst_p.

2007-07-24  Paolo Carlini  <pcarlini@suse.de>

	PR c++/32561
	* decl.c (redeclaration_error_message): Call DECL_ANON_UNION_VAR_P
	only on VAR_DECL.

/testsuite
2007-07-24  Paolo Carlini  <pcarlini@suse.de>

	PR c++/29001
	* g++.dg/init/new22.C: New.

2007-07-24  Paolo Carlini  <pcarlini@suse.de>

	PR c++/32561
	* g++.dg/template/crash67.C: New.

From-SVN: r126873

        * lib/target-support.exp (check_effective_target_natural_alignment):
        (check_effective_target_vector_alignment_reachable): New.
        * config/spu/spu.c (spu_vector_alignment_reachable): New.
        (TARGET_VECTOR_ALIGNMENT_REACHABLE): Define.
        * * gcc.dg/vect/pr25413a.c: Use vector_alignment_reachable target
        check.
        * gcc.dg/vect/pr25413.c: Likewise.
        * gcc.dg/vect/pr31699.c: Likewise.

From-SVN: r126872

From-SVN: r126869

2007-07-24  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/30814
	* trans-decl.c (generate_function_code):  Add argument
	for flag_bounds_check to the array for set_options.
	* invoke.texi:  Mention that some checks require
	-fbounds-check to be set during compilation of the
	main program.

2007-07-24  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/30814
	* libgfortran.h:  Add bounds_check to compile_options_t.
	* runtime/compile_options.c (set_options):  Add handling
	of compile_options.bounds_check.
	* intrinsics/pack_generic.c (pack_internal):  Also determine
	the number of elements if compile_options.bounds_check is
	true.  Raise runtime error if a different array shape is
	detected.

2007-07-24  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/30814
	* gfortran.dg/pack_bounds_1.f90:  New test case.

From-SVN: r126866

From-SVN: r126864

	* i386.c (ix86_secondary_memory_needed): Break out to...
	(inline_secondary_memory_needed): ... here.
	(ix86_memory_move_cost): Break out to ...
	(inline_memory_move_cost): ... here; add support for IN value of 2 for
	maximum of input and output; fix handling of Q_REGS on 64bit.
	(ix86_secondary_memory_needed): Microoptimize.

From-SVN: r126861

	* tree-data-ref.c (find_vertex_for_stmt, create_rdg_edge_for_ddr,
	create_rdg_edges_for_scalar, create_rdg_edges, create_rdg_vertices,
	stmts_from_loop, known_dependences_p, build_rdg): New.
	* tree-data-ref.h: Depends on graphds.h.
	(rdg_vertex, RDGV_STMT, rdg_dep_type, rdg_edge, RDGE_TYPE): New.
	(build_rdg): Declared.
	* Makefile.in (TREE_DATA_REF_H): Depends on graphds.h.

From-SVN: r126859

gcc/fortran:
2007-07-23  Daniel Franke  <franke.daniel@gmail.com>

	PR fortran/25104
	PR fortran/31639
	* expr.c (check_transformational): Reject valid transformational
	intrinsics to avoid ICE.
	(check_inquiry): Report error for assumed character lengths for
	all supported standards.
	(check_init_expr): Whitespace fix.

gcc/testsuite:
2007-07-23  Daniel Franke  <franke.daniel@gmail.com>

	PR fortran/31639
	* gfortran.dg/initialization_9.f90: New test.

From-SVN: r126858

2007-07-23  Daniel Berlin  <dberlin@dberlin.org>

	* tree-ssa-propagate.c (valid_gimple_expression_p): Match up with
	ccp_min_invariant.

From-SVN: r126857

2007-07-23  Christopher D. Rickett  <crickett@lanl.gov>

        PR fortran/32797
        PR fortran/32800
        * decl.c (verify_bind_c_sym): Use the result symbol for functions
        with a result clause.  Warn if implicitly typed.  Verify the type
        and rank of the SHAPE argument, if given.
        * resolve.c (gfc_iso_c_sub_interface): Use gfc_procedure_use to
        check the actual args against the formal, sorting them if
        necessary.
        * symbol.c (gen_shape_param): Initialize type of SHAPE param to
        BT_VOID.

2007-07-23  Christopher D. Rickett  <crickett@lanl.gov>

        PR fortran/32797
        PR fortran/32800
        * gfortran.dg/bind_c_usage_8.f03: New test case.
        * gfortran.dg/c_f_pointer_tests_2.f03: Ditto.
        * gfortran.dg/c_ptr_tests_5.f03: Updated expected error message.

From-SVN: r126856

* argv.c (writeargv): Fix typo in inline documentation.
* functions.texi: Regenerate.

From-SVN: r126855

	PR middle-end/PR28690
	* optabs.c (expand_binop): (emit_cmp_and_jump_insns): Allow EQ compares.
	* rtlanal.c (commutative_operand_precedence): Prefer both REG_POINTER
	and MEM_POINTER operands over REG and MEM operands.
	(swap_commutative_operands_p): Change return value to bool.
	* rtl.h: Update the corresponding prototype.
	* tree-ssa-address.c (gen_addr_rtx): Use simplify_gen_binary
	instead of gen_rtx_PLUS.
	* simplify-rtx.c (simplify_plus_minus_op_data_cmp): Change return
	value to bool.  Change function arguments to rtx's and update code
	to match.
	(simplify_plus_minus): Update the simplify_plus_minus_op_data_cmp
	calls to match the new declaration.
	* simplify-rtx.c (simplify_associative_operation): Don't
	reorder simplify_binary_operation arguments.

Co-Authored-By: Jakub Jelinek <jakub@redhat.com>

From-SVN: r126852

	* configure.ac (mips-sgi-irix6*): Override SYSTEMSPEC.
	* configure: Regenerate.

From-SVN: r126847

gcc/
	* config/mips/mips.c (override_options): Use mips_costs to derive
	the default branch cost.
	* config/mips/mips.h (BRANCH_COST): Use mips_branch_cost rather
	than mips_costs.
	* config/mips/mips.opt (mbranch-cost=): New option.
	* doc/invoke.texi (-mbrach-cost): Document new MIPS option.

gcc/testsuite/
	* gcc.target/mips/branch-cost-1.c: New test.
	* gcc.target/mips/branch-cost-2.c: Likewise.

From-SVN: r126846

From-SVN: r126845