Building for i686-mingw32 target (with some local changes) produced an
error

error: ISO C++ forbids declaration of 'lstat' with no type [-fpermissive]

in libstdc++-v3/src/filesystem/ops-common.h.  This patch adds the
missing return type.  OK to commit (trunk and GCC 9 branch)?

Note 1: I haven't run the testsuite with this patch, but it fixes the
build failure I see (in sources with other local changes).

Note 2: I don't know why this hasn't produced build failures for other
people, but the missing return type looks wrong in any case even if
other local changes are for some reason needed for it to produce an
error.

	* src/filesystem/ops-common.h [_GLIBCXX_FILESYSTEM_IS_WINDOWS]
	(std::filesystem::__gnu_posix::lstat): Add return type.

From-SVN: r274885

From-SVN: r274868

https://gcc.gnu.org/ml/gcc-patches/2019-08/msg01674.html
	* class.c (check_for_override): Checking IDENTIFIER_VIRTUAL_P is
	sufficient, reorder DECL_OVERRIDE_P check.

From-SVN: r274867

        * config/mips/mips.md (mips_get_fcsr, *mips_get_fcsr): Use SI
        machine mode for unspec_volatile operand.

        * gcc.target/mips/get-fcsr-3.c: New test.

From-SVN: r274863

gcc/testsuite/ChangeLog:

	* gcc.dg/pr78973.c: Make functions static to avoid failures
	with -fpic
	* gcc.dg/pr78973-2.c: Same.

From-SVN: r274860

gcc/testsuite/ChangeLog:

	* gcc.dg/Warray-bounds-36.c: Make functions static to avoid failures
	with -fpic.
	* gcc.dg/Warray-bounds-41.c: Same.

From-SVN: r274859

Deprecate -mneon-for-64bits since it no longer has any effect after
the DImode codegen improvements.

    gcc/
	* gcc/doc/invoke.texi (mneon-for-64bits): Deprecate option.
	* gcc/config/arm/arm.opt (mneon-for-64bits): Deprecate option.
	* gcc/config/arm/arm.h (TARGET_PREFER_NEON_64BITS): Remove.
	(prefer_neon_for_64bits): Remove.
	* gcc/config/arm/arm.c (prefer_neon_for_64bits): Remove.
	(tune_params): Remove PREF_NEON_64_FALSE uses.
	(arm_option_override): Remove prefer_neon selection code.
	(arm_print_tune_info): Remove prefer_neon_for_64bits.
	* gcc/config/arm/arm-protos.h (tune_params): Remove
	prefer_neon_for_64bits.
	(prefer_neon_for_64bits): Remove.

From-SVN: r274858

Prevent lines overlapping the right hand margin, this occurred for
references in the "See also:" section, it is prevented by placing
references on their own lines. Two example programs overlapped the
right hand margin: fixed by adjusting the position and of the comments.
Some tables had overlapping colums: the column widths were adjusted
accordingly.

From-SVN: r274857

When we are parsing a source file, the very first token might
be a PRAGMA_GCC_PCH_PREPROCESS.  This indicates that we are going
read in a PCH file (named as the value of the pragma).  If we don't
see this pragma, then we know that it's OK to release any resources
that the host might have set aside for the PCH file.

This fixes a thinko in the current implementation, in that the decision
to release resources was happening unconditionally right after the first
token is extracted but before it's been checked or acted upon.

This leads to the pch bug (seen on Darwin), because we actually do release
resources - which are subsequently (reasonably) assumed to be available
when reading a PCH file.  We then get random crashes or hangs depending
on the interaction between unmmap and malloc.

The bug is present everywhere but doesn't show on (say) Linux, since
the release of PCH resources is a NOP there.

This effects all the c-family front ends, because they all use c_lex_with_flags ()
to implement this.

The solution is to check for the PRAGMA_GCC_PCH_PREPROCESS and only call
c_common_no_more_pch () when that is not the first token.

A secondary effect of the collection is that the name of the PCH file
can be collected during the ggc_pch_read() reset of state.  Therefore
we should issue any diagnostic that might name the file before the
collections are triggered.


gcc/c-family/

2019-08-23  Iain Sandoe  <iain@sandoe.co.uk>

	PR pch/61250
	* c-lex.c (c_lex_with_flags):  Don't call
	c_common_no_more_pch () from here.

gcc/c/

2019-08-23  Iain Sandoe  <iain@sandoe.co.uk>

	PR pch/61250
	* c-parser.c (c_parse_file): Call c_common_no_more_pch ()
	after determining that the first token is not
	PRAGMA_GCC_PCH_PREPROCESS.

gcc/cp/

2019-08-23  Iain Sandoe  <iain@sandoe.co.uk>

	PR pch/61250
	* parser.c (cp_parser_initial_pragma): Call c_common_no_more_pch ()
	after determining that the first token is not
	PRAGMA_GCC_PCH_PREPROCESS.

gcc/

2019-08-23  Iain Sandoe  <iain@sandoe.co.uk>

	PR pch/61250
	* ggc-page.c (ggc_pch_read): Read the ggc_pch_ondisk structure
	and issue any diagnostics needed before collecting the pre-PCH
	state.

From-SVN: r274856

	PR middle-end/91283
	* common.opt (fexcess-precision=): Add Optimization flag.  Use
	flag_excess_precision variable instead of
	flag_excess_precision_cmdline.
	* flags.h (class target_flag_state): Remove x_flag_excess_precision
	member.
	(flag_excess_precision): Don't define.
	* langhooks.c (lhd_post_options): Set flag_excess_precision instead of
	flag_excess_precision_cmdline.  Remove comment.
	* opts.c (set_fast_math_flags): Use frontend_set_flag_excess_precision
	and x_flag_excess_precision instead of
	frontend_set_flag_excess_precision_cmdline and
	x_flag_excess_precision_cmdline.
	(fast_math_flags_set_p): Use x_flag_excess_precision instead of
	x_flag_excess_precision_cmdline.
	* toplev.c (init_excess_precision): Remove.
	(lang_dependent_init_target): Don't call it.
ada/
	* gcc-interface/misc.c (gnat_post_options): Set flag_excess_precision
	instead of flag_excess_precision_cmdline.
brig/
	* brig-lang.c (brig_langhook_post_options): Set flag_excess_precision
	instead of flag_excess_precision_cmdline.
c-family/
	* c-common.c (c_ts18661_flt_eval_method): Use flag_excess_precision
	instead of flag_excess_precision_cmdline.
	* c-cppbuiltin.c (c_cpp_flt_eval_method_iec_559): Likewise.
	* c-opts.c (c_common_post_options): Likewise.
d/
	* d-lang.cc (d_post_options): Set flag_excess_precision instead of
	flag_excess_precision_cmdline.
fortran/
	* options.c (gfc_post_options): Set flag_excess_precision instead of
	flag_excess_precision_cmdline.  Remove comment.
go/
	* go-lang.c (go_langhook_post_options): Set flag_excess_precision
	instead of flag_excess_precision_cmdline.
lto/
	* lto-lang.c (lto_post_options): Set flag_excess_precision instead of
	flag_excess_precision_cmdline.  Remove comment.

From-SVN: r274850

2019-08-23  Martin Liska  <mliska@suse.cz>

	* lto-wrapper.c (run_gcc): When setting jobserver
	set also parallel to 1.  This was done so before r273908.

From-SVN: r274849

Documentation of all intrinsics now have their sections in a consistent
order. Empty sections have been removed. Stray words have been removed.
Text in a wrong section has been moved.  A missing standard was inserted.

From-SVN: r274848

The specific intrinsics ZABS and CDABS return REAL(8) not COMPLEX(8).

From-SVN: r274847

re PR target/91306 ([MSP430] libgcc/crtstuff.c: Alignment of frame_dummy .init_array entry is too big)

2019-08-23  Jozef Lawrynowicz  <jozef.l@mittosystems.com>

	PR target/91306
	* crtstuff.c (__CTOR_LIST__): Align to the "__alignof__" the array
	element type, instead of "sizeof" the element type.
	(__DTOR_LIST__): Likewise.
	(__TMC_LIST__): Likewise.
	(__do_global_dtors_aux_fini_array_entry): Likewise.
	(__frame_dummy_init_array_entry): Likewise.
	(__CTOR_END__): Likewise.
	(__DTOR_END__): Likweise.
	(__FRAME_END__): Likewise.
	(__TMC_END__): Likewise.

From-SVN: r274846

This patch adds '-mcpu' options for following CPUs:
Cortex-M35P, Cortex-A77, Cortex-A76AE.

Related specifications are as following:
https://developer.arm.com/ip-products/processors/cortex-m
https://developer.arm.com/ip-products/processors/cortex-a

2019-08-23  Dennis Zhang  <dennis.zhang@arm.com>

	* config/arm/arm-cpus.in (cortex-m35p): New entry.
	(cortex-a76ae): Likewise.
	(cortex-a77): Likewise
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Likewise.
	* doc/invoke.texi (ARM Options): Document cortex-m35p, cortx-a76ae,
	cortex-a77 CPU options.

From-SVN: r274845

2019-08-23  Martin Liska  <mliska@suse.cz>

	* profile.c (instrument_values): Do not set
	0 as last argument.
	* tree-profile.c (gimple_gen_interval_profiler): Remove
	last argument.
	(gimple_gen_pow2_profiler): Likewise.
	(gimple_gen_topn_values_profiler): Likewise.
	(gimple_gen_ic_profiler): Likewise.
	(gimple_gen_time_profiler): Likewise.
	(gimple_gen_average_profiler): Likewise.
	(gimple_gen_ior_profiler): Likewise.
	* value-prof.c (dump_histogram_value): Use default
	in switch statement instead of HIST_TYPE_MAX.
	(stream_in_histogram_value): Likewise.
	(gimple_duplicate_stmt_histograms): Do not
	use NULL for implicitly set arguments.
	(gimple_divmod_values_to_profile): Do not use
	reserve+quick_push.
	(gimple_indirect_call_to_profile): Likewise.
	(gimple_find_values_to_profile): Use implicit
	function call arguments.
	* value-prof.h (gimple_alloc_histogram_value):
	Set default values.
	(gimple_gen_interval_profiler): Remove last argument.
	(gimple_gen_pow2_profiler): Likewise.
	(gimple_gen_topn_values_profiler): Likewise.
	(gimple_gen_ic_profiler): Likewise.
	(gimple_gen_time_profiler): Likewise.
	(gimple_gen_average_profiler): Likewise.
	(gimple_gen_ior_profiler): Likewise.

From-SVN: r274844

From-SVN: r274843

	* parser.c (cp_parser_condition): Handle prefix attributes.

	* g++.dg/cpp0x/gen-attrs-70.C: New test.

From-SVN: r274839

intrinsic.c (add_subroutines): ERRMSG is INTENT(INOUT) in co_broadcast, co_max, co_min, co_reduce, and co_sum.

2019-08-22  Steven G. Kargl  <kargl@gcc.gnu.org>

	* intrinsic.c (add_subroutines): ERRMSG is INTENT(INOUT) in
	co_broadcast, co_max, co_min, co_reduce, and  co_sum.

From-SVN: r274838

PR middle-end/91490 - bogus argument missing terminating nul warning on strlen of a flexible array member

gcc/c-family/ChangeLog:

	PR middle-end/91490
	* c-common.c (braced_list_to_string): Add argument and overload.
	Handle flexible length arrays and unions.

gcc/testsuite/ChangeLog:

	PR middle-end/91490
	* c-c++-common/Warray-bounds-7.c: New test.
	* gcc.dg/Warray-bounds-39.c: Expect either -Warray-bounds or
	-Wstringop-overflow.
	* gcc.dg/strlenopt-78.c: New test.

gcc/ChangeLog:

	PR middle-end/91490
	* builtins.c (c_strlen): Rename argument and introduce new local.
	Set no-warning bit on original argument.
	* expr.c (string_constant): Pass argument type to fold_ctor_reference.
	Fold empty and zero constructors into empty strings.
	* gimple-fold.c (fold_nonarray_ctor_reference): Return a STRING_CST
	for missing initializers.
	* tree.c (build_string_literal): Handle optional argument.
	* tree.h (build_string_literal): Add defaulted argument.
	* gimple-ssa-warn-restrict.c (maybe_diag_access_bounds): Check
	no-warning bit on original expression.

From-SVN: r274837

	* gcc.target/i386/minmax-4.c: Add -mno-stackrealign to dg-options.
	* gcc.target/i386/minmax-5.c: Likewise.
	* gcc.target/i386/minmax-6.c: Likewise.
	* gcc.target/i386/minmax-7.c: Likewise.
	* gcc.target/i386/pr91154.c: Likewise.

From-SVN: r274836

Every call to darn should deliver a *new* random number; such calls
should not be CSEd together.  So they should be unspec_volatile, not
plain unspec.


	PR target/91481
	* config/rs6000/rs6000.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32,
	and UNSPEC_DARN_RAW.
	(unspecv): New enumerator values UNSPECV_DARN, UNSPECV_DARN_32, and
	UNSPECV_DARN_RAW.
	(darn_32): Use an unspec_volatile, and UNSPECV_DARN_32.
	(darn_raw): Use an unspec_volatile, and UNSPECV_DARN_RAW.
	(darn): Use an unspec_volatile, and UNSPECV_DARN.

From-SVN: r274835

	* config/rs6000/altivec.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32,
	UNSPEC_DARN_RAW, UNSPEC_CMPRB, UNSPEC_CMPRB2, UNSPEC_CMPEQB; move to...
	* config/rs6000/rs6000.md (unspec): ... here.
	* config/rs6000/altivec.md (darn_32, darn_raw, darn, cmprb,
	*cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal,
	cmpeqb, *cmpeqb_internal): Delete, move to...
	* config/rs6000/rs6000.md (darn_32, darn_raw, darn, cmprb,
	*cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal,
	cmpeqb, *cmpeqb_internal): ... here.

From-SVN: r274834

c-parser.c (c_parser_declaration_or_fndef): Set DECL_ARGUMENTS of a FUNCTION_DECL to the right value in the presence of...

	* c-parser.c (c_parser_declaration_or_fndef): Set DECL_ARGUMENTS of a
	FUNCTION_DECL to the right value in the presence of nested declarators.

From-SVN: r274828

We currently have a nasty error when trying to use the __crc* intrinsics
with an -mfloat-abi=hard.
That is because the target pragma guarding them uses armv8-a+crc that
does not include fp by default.
So we get errors like:
error: '-mfloat-abi=hard': selected processor lacks an FPU

This patch fixes that by using an FP-enabled arch target pragma to guard
these intrinsics when floating-point is available.
That way both the softfloat and hardfloat variants work.

     * config/arm/arm_acle.h: Use arch=armv8-a+crc+simd pragma for CRC32
     intrinsics if __ARM_FP.
     Use __ARM_FEATURE_CRC32 ifdef guard.

     * gcc.target/arm/acle/crc_hf_1.c: New test.

From-SVN: r274827

Remove the remaining Neon adddi3, subdi3 and negdi2 patterns.  As a result
adddi3, subdi3 and negdi2 can now always be expanded early irrespectively of
whether Neon is available.  Also expand the extenddi patterns at the same
time.  Several Neon arch attributes are no longer used and removed.

Code generation is improved in all cases, saving another 400-500 instructions
from the PR77308 testcase (total improvement is over 1700 instructions with
-mcpu=cortex-a57 -O2).

Bootstrap & regress OK on arm-none-linux-gnueabihf --with-cpu=cortex-a57

    gcc/
	* config/arm/arm.md (neon_for_64bits): Remove.
	(avoid_neon_for_64bits): Remove.
	(arm_adddi3): Always split early.
	(arm_subdi3): Always split early.
	(negdi2): Remove Neon expansion.
	(split zero_extend): Split before reload.
	(split sign_extend): Split before reload.

From-SVN: r274825

Like the logical operations, expand all shifts early rather than only
sometimes.  The Neon shift expansions are never emitted (not even with
-fneon-for-64bits), so they are not useful.  So all the late expansions
and Neon shift patterns can be removed, and shifts are more optimized
as a result.  Since some extend patterns use Neon DImode shifts, remove
the Neon extend variants and related splits.

A simple example now generates the same efficient code after this
patch with -mfpu=neon and -mfpu=vfp (previously just the fact of
having Neon enabled resulted inefficient code for no reason).

unsigned long long f(unsigned long long x, unsigned long long y)
{ return x & (y >> 33); }

Before:
	strd    r4, r5, [sp, #-8]!
	lsr     r4, r3, #1
	mov     r5, #0
	and     r1, r1, r5
	and     r0, r0, r4
	ldrd    r4, r5, [sp]
	add     sp, sp, #8
	bx      lr

After:
	and     r0, r0, r3, lsr #1
	mov     r1, #0
	bx      lr

Bootstrap and regress OK on arm-none-linux-gnueabihf --with-cpu=cortex-a57

    gcc/
	* config/arm/iterators.md (qhs_extenddi_cstr): Update.
	(qhs_extenddi_cstr): Likewise.
	* config/arm/arm.md (ashldi3): Always expand early.
	(ashlsi3): Likewise.
	(ashrsi3): Likewise.
	(zero_extend<mode>di2): Remove Neon variants.
	(extend<mode>di2): Likewise.
	* config/arm/neon.md (ashldi3_neon_noclobber): Remove.
	(signed_shift_di3_neon): Likewise.
	(unsigned_shift_di3_neon): Likewise.
	(ashrdi3_neon_imm_noclobber): Likewise.
	(lshrdi3_neon_imm_noclobber): Likewise.
	(<shift>di3_neon): Likewise.
	(split extend): Remove DI extend split patterns.

   gcc/testsuite/
	* gcc.target/arm/neon-extend-1.c: Remove test.
	* gcc.target/arm/neon-extend-2.c: Remove test.

From-SVN: r274824

Cleanup the logical DImode operations since the current implementation is way
too complicated.  Thumb-1, Thumb-2, VFP/Neon and iwMMXt all work differently,
resulting in a bewildering number of expansions, patterns and splits across
several md files.  All this complexity is counterproductive and results in
inefficient code.

A much simpler approach is to split these operations early in the expander
so that optimizations and register allocation are applied on the 32-bit halves.
Codegeneration is unchanged on Thumb-1 and Arm/Thumb-2 without Neon or iwMMXt
(which already expand these instructions early).  With Neon these changes save
~1000 instructions from the PR77308 testcase, mostly by significantly reducing
register pressure and spilling.

Bootstrap OK on arm-none-linux-gnueabihf --with-cpu=cortex-a57

    gcc/
	* config/arm/arm.md (split and/eor/ior): Remove Neon check.
	(split not): Add DImode not splitter.
	(anddi3): Remove pattern.
	(anddi3_insn): Likewise.
	(anddi_zesidi_di): Likewise.
	(anddi_sesdi_di): Likewise.
	(anddi_notdi_di): Likewise.
	(anddi_notzesidi_di): Likewise.
	(anddi_notsesidi_di): Likewise.
	(iordi3): Likewise.
	(iordi3_insn): Likewise.
	(iordi_zesidi_di): Likewise.
	(iordi_sesidi_di): Likewise.
	(xordi3): Likewise.
	(xordi3_insn): Likewise.
	(xordi_sesidi_di): Likewise.
	(xordi_zesidi_di): Likewise.
	(one_cmpldi2): Likewise.
	(one_cmpldi2_insn): Likewise.
	* config/arm/constraints.md: Remove De, Df, Dg constraints.
	* config/arm/iwmmxt.md (iwmmxt_iordi3): Remove general register
	alternative.
	(iwmmxt_xordi3): Likewise.
	(iwmmxt_anddi3): Likewise.
	* config/arm/neon.md (orndi3_neon): Remove pattern.
	(anddi_notdi_di): Likewise.
	* config/arm/predicates.md (arm_anddi_operand_neon): Remove.
	(arm_iordi_operand_neon): Likewise.
	(arm_xordi_operand_neon): Likewise.
	* config/arm/thumb2.md(iordi_notdi_di): Remove pattern.
	(iordi_notzesidi_di): Likewise.
	(iordi_notdi_zesidi): Likewise.
	(iordi_notsesidi_di): Likewise.

From-SVN: r274823

The iorsi3_compare0 and iorsi3_compare0_scratch patterns can make use
of the 16-bit thumb orrs instruction if suitable registers are
allocated.  This patch adds the alternative to allow this to happen.

	* config/arm/arm.md (iorsi3_compare0): Add alternative for 16-bit thumb
	insn.
	(iorsi3_compare0_scratch): Likewise.

From-SVN: r274822

This patch adds the intrinsic functions for:
- vld1_<mode>_x4
- vst1_<mode>_x4
- vld1q_<mode>_x4
- vst1q_<mode>_x4

Bootstrapped and tested on aarch64-none-linux-gnu.

Committed on behalf of Sylvia Taylor.

2019-08-22  Sylvia Taylor  <sylvia.taylor@arm.com>

	* config/aarch64/aarch64-simd-builtins.def:
	(ld1x4): New.
	(st1x4): Likewise.
	* config/aarch64/aarch64-simd.md:
	(aarch64_ld1x4<VALLDIF:mode>): New pattern.
	(aarch64_st1x4<VALLDIF:mode>): Likewise.
	(aarch64_ld1_x4_<mode>): Likewise.
	(aarch64_st1_x4_<mode>): Likewise.
	* config/aarch64/arm_neon.h:
	(vld1_s8_x4): New function.
	(vld1q_s8_x4): Likewise.
	(vld1_s16_x4): Likewise.
	(vld1q_s16_x4): Likewise.
	(vld1_s32_x4): Likewise.
	(vld1q_s32_x4): Likewise.
	(vld1_u8_x4): Likewise.
	(vld1q_u8_x4): Likewise.
	(vld1_u16_x4): Likewise.
	(vld1q_u16_x4): Likewise.
	(vld1_u32_x4): Likewise.
	(vld1q_u32_x4): Likewise.
	(vld1_f16_x4): Likewise.
	(vld1q_f16_x4): Likewise.
	(vld1_f32_x4): Likewise.
	(vld1q_f32_x4): Likewise.
	(vld1_p8_x4): Likewise.
	(vld1q_p8_x4): Likewise.
	(vld1_p16_x4): Likewise.
	(vld1q_p16_x4): Likewise.
	(vld1_s64_x4): Likewise.
	(vld1_u64_x4): Likewise.
	(vld1_p64_x4): Likewise.
	(vld1q_s64_x4): Likewise.
	(vld1q_u64_x4): Likewise.
	(vld1q_p64_x4): Likewise.
	(vld1_f64_x4): Likewise.
	(vld1q_f64_x4): Likewise.
	(vst1_s8_x4): Likewise.
	(vst1q_s8_x4): Likewise.
	(vst1_s16_x4): Likewise.
	(vst1q_s16_x4): Likewise.
	(vst1_s32_x4): Likewise.
	(vst1q_s32_x4): Likewise.
	(vst1_u8_x4): Likewise.
	(vst1q_u8_x4): Likewise.
	(vst1_u16_x4): Likewise.
	(vst1q_u16_x4): Likewise.
	(vst1_u32_x4): Likewise.
	(vst1q_u32_x4): Likewise.
	(vst1_f16_x4): Likewise.
	(vst1q_f16_x4): Likewise.
	(vst1_f32_x4): Likewise.
	(vst1q_f32_x4): Likewise.
	(vst1_p8_x4): Likewise.
	(vst1q_p8_x4): Likewise.
	(vst1_p16_x4): Likewise.
	(vst1q_p16_x4): Likewise.
	(vst1_s64_x4): Likewise.
	(vst1_u64_x4): Likewise.
	(vst1_p64_x4): Likewise.
	(vst1q_s64_x4): Likewise.
	(vst1q_u64_x4): Likewise.
	(vst1q_p64_x4): Likewise.
	(vst1_f64_x4): Likewise.
	(vst1q_f64_x4): Likewise.

	* gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vst1x4.c: New test.

From-SVN: r274820

2019-08-22  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

	* config/aarch64/aarch64-sve.md (vcond_mask): Add "@".

From-SVN: r274817

From-SVN: r274816

2019-08-22  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
	    Richard Sandiford  <richard.sandiford@arm.com>

	PR target/88839
	* config/aarch64/aarch64.c (aarch64_evpc_sel): New function.
	(aarch64_expand_vec_perm_const_1): Call aarch64_evpc_sel.

testsuite/
	* gcc.target/aarch64/sve/sel_1.c: New test.
	* gcc.target/aarch64/sve/sel_2.c: Likewise.
	* gcc.target/aarch64/sve/sel_3.c: Likewise.
	* gcc.target/aarch64/sve/sel_4.c: Likewise.
	* gcc.target/aarch64/sve/sel_5.c: Likewise.
	* gcc.target/aarch64/sve/sel_6.c: Likewise.

Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com>

From-SVN: r274810

2019-08-21  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

	PR target/90724
	* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): Force y
	in reg if it fails aarch64_plus_operand predicate.

From-SVN: r274805

    
    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/191040

From-SVN: r274803

    
    Fixes golang/go#33739
    
    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/191037

From-SVN: r274800

copy_attributes_to_builtin only handles BUILT_IN_NORMAL, but C++ was
calling it immediately after the:

	  if (DECL_BUILT_IN_CLASS (newdecl) == BUILT_IN_NORMAL)

block.  The corresponding C code calls it inside the block instead.

2019-08-21  Richard Sandiford  <richard.sandiford@arm.com>

gcc/cp/
	PR c++/91505
	* decl.c (duplicate_decls): Call copy_attributes_to_builtin inside
	the BUILT_IN_NORMAL block rather than afterward.

gcc/testsuite/
	PR c++/91505
	* g++.target/i386/crc32-4.C: New test.

From-SVN: r274799

2019-08-21  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/91482
	* tree-ssa-ccp.c (ccp_folder::fold_stmt): Remove useless
	BUILT_IN_ASSUME_ALIGNED calls.

	* gcc.dg/tree-ssa/pr91482.c: New testcase.

From-SVN: r274796

c-ada-spec.c (dump_ada_function_declaration): Be prepared for broken function declarations where arguments are missing.

	* c-ada-spec.c (dump_ada_function_declaration): Be prepared for broken
	function declarations where arguments are missing.  Rename variables.

From-SVN: r274794

2019-08-21  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/arm/cmse/cmse-9.c: Add quotes to expected
	warning messages.

From-SVN: r274793