PR ipa/83178
	* g++.dg/ipa/devirt-22.C: Adjust scan-dump-times count.

From-SVN: r256542

	PR tree-optimization/83695
	* gimple-loop-linterchange.cc
	(tree_loop_interchange::interchange_loops): Call scev_reset_htab to
	reset cached scev information after interchange.
	(pass_linterchange::execute): Remove call to scev_reset_htab.

	gcc/testsuite
	PR tree-optimization/83695
	* gcc.dg/tree-ssa/pr83695.c: New test.

From-SVN: r256541

This patch implements the lane-wise fp16fml intrinsics.
There's quite a few of them so I've split them up from
the other simpler fp16fml intrinsics.

These ones expose instructions such as

vfmal.f16 Dd, Sn, Sm[<index>]  0 <= index <= 1
vfmal.f16 Qd, Dn, Dm[<index>]  0 <= index <= 3
vfmsl.f16 Dd, Sn, Sm[<index>]  0 <= index <= 1
vfmsl.f16 Qd, Dn, Dm[<index>]  0 <= index <= 3

These instructions extract a single half-precision
floating-point value from one of the source regs
and perform a vfmal/vfmsl operation as per the
normal variant with that value.

The nuance here is that some of the intrinsics want
to do things like:

float32x2_t vfmlal_laneq_low_u32 (float32x2_t __r, float16x4_t __a, float16x8_t __b, const int __index)


where the float16x8_t value of '__b' is held in a Q
register, so we need to be a bit smart about finding
the right D or S sub-register and translating the
lane number to a lane in that sub-register, instead
of just passing the language-level const-int down to
the assembly instruction.

That's where most of the complexity of this patch comes from
but hopefully it's orthogonal enough to make sense.

Bootstrapped and tested on arm-none-linux-gnueabihf as well as
armeb-none-eabi.

	* config/arm/arm_neon.h (vfmlal_lane_low_u32, vfmlal_lane_high_u32,
	vfmlalq_laneq_low_u32, vfmlalq_lane_low_u32, vfmlal_laneq_low_u32,
	vfmlalq_laneq_high_u32, vfmlalq_lane_high_u32, vfmlal_laneq_high_u32,
	vfmlsl_lane_low_u32, vfmlsl_lane_high_u32, vfmlslq_laneq_low_u32,
	vfmlslq_lane_low_u32, vfmlsl_laneq_low_u32, vfmlslq_laneq_high_u32,
	vfmlslq_lane_high_u32, vfmlsl_laneq_high_u32): Define.
	* config/arm/arm_neon_builtins.def (vfmal_lane_low,
	vfmal_lane_lowv4hf, vfmal_lane_lowv8hf, vfmal_lane_high,
	vfmal_lane_highv4hf, vfmal_lane_highv8hf, vfmsl_lane_low,
	vfmsl_lane_lowv4hf, vfmsl_lane_lowv8hf, vfmsl_lane_high,
	vfmsl_lane_highv4hf, vfmsl_lane_highv8hf): New sets of builtins.
	* config/arm/iterators.md (VFMLSEL2, vfmlsel2): New mode attributes.
	(V_lane_reg): Likewise.
	* config/arm/neon.md (neon_vfm<vfml_op>l_lane_<vfml_half><VCVTF:mode>):
	New define_expand.
	(neon_vfm<vfml_op>l_lane_<vfml_half><vfmlsel2><mode>): Likewise.
	(vfmal_lane_low<mode>_intrinsic,
	vfmal_lane_low<vfmlsel2><mode>_intrinsic,
	vfmal_lane_high<vfmlsel2><mode>_intrinsic,
	vfmal_lane_high<mode>_intrinsic, vfmsl_lane_low<mode>_intrinsic,
	vfmsl_lane_low<vfmlsel2><mode>_intrinsic,
	vfmsl_lane_high<vfmlsel2><mode>_intrinsic,
	vfmsl_lane_high<mode>_intrinsic): New define_insns.

	* gcc.target/arm/simd/fp16fml_lane_high.c: New test.
	* gcc.target/arm/simd/fp16fml_lane_low.c: New test.

From-SVN: r256540

This patch adds the +fp16fml extension that enables some
half-precision floating-point Advanced SIMD instructions,
available through arm_neon.h intrinsics.

This extension is on by default for armv8.4-a
if fp16 is available, so it can be enabled by -march=armv8.4-a+fp16.

fp16fml is also available for armv8.2-a and armv8.3-a through the
+fp16fml option that is added for these architectures.

The new instructions that this patch adds support for are:
vfmal.f16 Dr, Sm, Sn
vfmal.f16 Qr, Dm, Dn
vfmsl.f16 Dr, Sm, Sn
vfmsl.f16 Qr, Dm, Dn

They interpret their input registers as a vector of half-precision
floating-point values, extend them to single-precision vectors
and perform a fused multiply-add or subtract of them with the
destination vector.

This patch exposes these instructions through arm_neon.h intrinsics.
The set of intrinsics allows us to do stuff such as perform
the multiply-add/subtract operation on the low or top half of
float16x4_t and float16x8_t values.  This maps naturally in aarch64
to the FMLAL and FMLAL2 instructions but on arm we have to use the
fact that consecutive NEON registers overlap the wider register
(i.e. d0 is s0 plus s1, q0 is d0 plus d1 etc). This just means
we have to be careful to use the right subreg operand print code.

New arm-specific builtins are defined to expand to the new patterns.
I've managed to compress the define_expands using code, mode and int
iterators but the define_insns don't compress very well without two-tiered
iterators (iterator attributes expanding to iterators) which we
don't support.

Bootstrapped and tested on arm-none-linux-gnueabihf and also on
armeb-none-eabi.

	* config/arm/arm-cpus.in (fp16fml): New feature.
	(ALL_SIMD): Add fp16fml.
	(armv8.2-a): Add fp16fml as an option.
	(armv8.3-a): Likewise.
	(armv8.4-a): Add fp16fml as part of fp16.
	* config/arm/arm.h (TARGET_FP16FML): Define.
	* config/arm/arm-c.c (arm_cpu_builtins): Define __ARM_FEATURE_FP16_FML
	when appropriate.
	* config/arm/arm-modes.def (V2HF): Define.
	* config/arm/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32,
	vfmlal_high_u32, vfmlsl_high_u32, vfmlalq_low_u32,
	vfmlslq_low_u32, vfmlalq_high_u32, vfmlslq_high_u32): Define.
	* config/arm/arm_neon_builtins.def (vfmal_low, vfmal_high,
	vfmsl_low, vfmsl_high): New set of builtins.
	* config/arm/iterators.md (PLUSMINUS): New code iterator.
	(vfml_op): New code attribute.
	(VFMLHALVES): New int iterator.
	(VFML, VFMLSEL): New mode attributes.
	(V_reg): Define mapping for V2HF.
	(V_hi, V_lo): New mode attributes.
	(VF_constraint): Likewise.
	(vfml_half, vfml_half_selector): New int attributes.
	* config/arm/neon.md (neon_vfm<vfml_op>l_<vfml_half><mode>): New
	define_expand.
	(vfmal_low<mode>_intrinsic, vfmsl_high<mode>_intrinsic,
	vfmal_high<mode>_intrinsic, vfmsl_low<mode>_intrinsic):
	New define_insn.
	* config/arm/t-arm-elf (v8_fps): Add fp16fml.
	* config/arm/t-multilib (v8_2_a_simd_variants): Add fp16fml.
	* config/arm/unspecs.md (UNSPEC_VFML_LO, UNSPEC_VFML_HI): New unspecs.
	* doc/invoke.texi (ARM Options): Document fp16fml.  Update armv8.4-a
	documentation.
	* doc/sourcebuild.texi (arm_fp16fml_neon_ok, arm_fp16fml_neon):
	Document new effective target and option set.

	* gcc.target/arm/multilib.exp: Add combination tests for fp16fml.
	* gcc.target/arm/simd/fp16fml_high.c: New test.
	* gcc.target/arm/simd/fp16fml_low.c: Likewise.
	* lib/target-supports.exp
	(check_effective_target_arm_fp16fml_neon_ok_nocache,
	check_effective_target_arm_fp16fml_neon_ok,
	add_options_for_arm_fp16fml_neon): New procedures.

From-SVN: r256539

This patch adds support for the Armv8.4-A architecture [1]
in the arm backend. This is done through the new
-march=armv8.4-a option.

With this patch armv8.4-a is recognised as an argument
and supports the extensions: simd, fp16, crypto, nocrypto,
nofp with the familiar meaning of these options.
Worth noting that there is no dotprod option like in
armv8.2-a and armv8.3-a because Dot Product support is
mandatory in Armv8.4-A when simd is available, so when using
+simd (of fp16 which enables +simd), the +dotprod is implied.

The various multilib selection makefile fragments are updated
too and the mutlilib.exp test gets a few armv8.4-a combination
tests.

Bootstrapped and tested on arm-none-linux-gnueabihf.

From-SVN: r256537

gcc/
	PR target/81821
	* config/rx/rx.md (BW): New mode attribute.
	(sync_lock_test_and_setsi): Add mode suffix to insn output.

From-SVN: r256536

2018-01-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/83435
	* graphite.c (canonicalize_loop_form): Ignore fake loop exit edges.
	* graphite-scop-detection.c (scop_detection::get_sese): Likewise.
	* tree-vrp.c (add_assert_info): Drop TREE_OVERFLOW if they appear.

	* gcc.dg/graphite/pr83435.c: New testcase.

From-SVN: r256535

This patch records the integer value of the address offset in
aarch64_address_info, so that it doesn't need to be re-extracted
from the rtx.  The SVE port will make more use of this.  The patch
also uses poly_int64 routines to manipulate the offset, rather than
just handling CONST_INTs.

2018-01-11  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_address_info): Add a const_offset
	field.
	(aarch64_classify_address): Initialize it.  Track polynomial offsets.
	(aarch64_print_address_internal): Use it to check for a zero offset.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r256534

This patch switches the AArch64 port to use 2 poly_int coefficients
and updates code as necessary to keep it compiling.

One potentially-significant change is to
aarch64_hard_regno_caller_save_mode.  The old implementation
was written in a pretty conservative way: it changed the default
behaviour for single-register values, but used the default handling
for multi-register values.

I don't think that's necessary, since the interesting cases for this
macro are usually the single-register ones.  Multi-register modes take
up the whole of the constituent registers and the move patterns for all
multi-register modes should be equally good.

Using the original mode for multi-register cases stops us from using
SVE modes to spill multi-register NEON values.  This was caught by
gcc.c-torture/execute/pr47538.c.

Also, aarch64_shift_truncation_mask used GET_MODE_BITSIZE - 1.
GET_MODE_UNIT_BITSIZE - 1 is equivalent for the cases that it handles
(which are all scalars), and I think it's more obvious, since if we ever
do use this for elementwise shifts of vector modes, the mask will depend
on the number of bits in each element rather than the number of bits in
the whole vector.

2018-01-11  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-modes.def (NUM_POLY_INT_COEFFS): Set to 2.
	* config/aarch64/aarch64-protos.h (aarch64_initial_elimination_offset):
	Return a poly_int64 rather than a HOST_WIDE_INT.
	(aarch64_offset_7bit_signed_scaled_p): Take the offset as a poly_int64
	rather than a HOST_WIDE_INT.
	* config/aarch64/aarch64.h (aarch64_frame): Protect with
	HAVE_POLY_INT_H rather than HOST_WIDE_INT.  Change locals_offset,
	hard_fp_offset, frame_size, initial_adjust, callee_offset and
	final_offset from HOST_WIDE_INT to poly_int64.
	* config/aarch64/aarch64-builtins.c (aarch64_simd_expand_args): Use
	to_constant when getting the number of units in an Advanced SIMD
	mode.
	(aarch64_builtin_vectorized_function): Check for a constant number
	of units.
	* config/aarch64/aarch64-simd.md (mov<mode>): Handle polynomial
	GET_MODE_SIZE.
	(aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>): Use the nunits
	attribute instead of GET_MODE_NUNITS.
	* config/aarch64/aarch64.c (aarch64_hard_regno_nregs)
	(aarch64_class_max_nregs): Use the constant_lowest_bound of the
	GET_MODE_SIZE for fixed-size registers.
	(aarch64_const_vec_all_same_in_range_p): Use const_vec_duplicate_p.
	(aarch64_hard_regno_call_part_clobbered, aarch64_classify_index)
	(aarch64_mode_valid_for_sched_fusion_p, aarch64_classify_address)
	(aarch64_legitimize_address_displacement, aarch64_secondary_reload)
	(aarch64_print_operand, aarch64_print_address_internal)
	(aarch64_address_cost, aarch64_rtx_costs, aarch64_register_move_cost)
	(aarch64_short_vector_p, aapcs_vfp_sub_candidate)
	(aarch64_simd_attr_length_rglist, aarch64_operands_ok_for_ldpstp):
	Handle polynomial GET_MODE_SIZE.
	(aarch64_hard_regno_caller_save_mode): Likewise.  Return modes
	wider than SImode without modification.
	(tls_symbolic_operand_type): Use strip_offset instead of split_const.
	(aarch64_pass_by_reference, aarch64_layout_arg, aarch64_pad_reg_upward)
	(aarch64_gimplify_va_arg_expr): Assert that we don't yet handle
	passing and returning SVE modes.
	(aarch64_function_value, aarch64_layout_arg): Use gen_int_mode
	rather than GEN_INT.
	(aarch64_emit_probe_stack_range): Take the size as a poly_int64
	rather than a HOST_WIDE_INT, but call sorry if it isn't constant.
	(aarch64_allocate_and_probe_stack_space): Likewise.
	(aarch64_layout_frame): Cope with polynomial offsets.
	(aarch64_save_callee_saves, aarch64_restore_callee_saves): Take the
	start_offset as a poly_int64 rather than a HOST_WIDE_INT.  Track
	polynomial offsets.
	(offset_9bit_signed_unscaled_p, offset_12bit_unsigned_scaled_p)
	(aarch64_offset_7bit_signed_scaled_p): Take the offset as a
	poly_int64 rather than a HOST_WIDE_INT.
	(aarch64_get_separate_components, aarch64_process_components)
	(aarch64_expand_prologue, aarch64_expand_epilogue)
	(aarch64_use_return_insn_p): Handle polynomial frame offsets.
	(aarch64_anchor_offset): New function, split out from...
	(aarch64_legitimize_address): ...here.
	(aarch64_builtin_vectorization_cost): Handle polynomial
	TYPE_VECTOR_SUBPARTS.
	(aarch64_simd_check_vect_par_cnst_half): Handle polynomial
	GET_MODE_NUNITS.
	(aarch64_simd_make_constant, aarch64_expand_vector_init): Get the
	number of elements from the PARALLEL rather than the mode.
	(aarch64_shift_truncation_mask): Use GET_MODE_UNIT_BITSIZE
	rather than GET_MODE_BITSIZE.
	(aarch64_evpc_trn, aarch64_evpc_uzp, aarch64_evpc_ext)
	(aarch64_evpc_rev, aarch64_evpc_dup, aarch64_evpc_zip)
	(aarch64_expand_vec_perm_const_1): Handle polynomial
	d->perm.length () and d->perm elements.
	(aarch64_evpc_tbl): Likewise.  Use nelt rather than GET_MODE_NUNITS.
	Apply to_constant to d->perm elements.
	(aarch64_simd_valid_immediate, aarch64_vec_fpconst_pow_of_2): Handle
	polynomial CONST_VECTOR_NUNITS.
	(aarch64_move_pointer): Take amount as a poly_int64 rather
	than an int.
	(aarch64_progress_pointer): Avoid temporary variable.
	* config/aarch64/aarch64.md (aarch64_<crc_variant>): Use
	the mode attribute instead of GET_MODE.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r256533

The port had aarch64_add_offset and aarch64_add_constant routines
that did similar things.  This patch replaces them with an expanded
version of aarch64_add_offset that takes separate source and
destination registers.  The new routine also takes a poly_int64 offset
instead of a HOST_WIDE_INT offset, but it leaves the HOST_WIDE_INT
case to aarch64_add_offset_1, which is basically a repurposed
aarch64_add_constant_internal.  The SVE patch will put the handling
of VL-based constants in aarch64_add_offset, while still using
aarch64_add_offset_1 for the constant part.

The vcall_offset == 0 path in aarch64_output_mi_thunk will use temp0
as well as temp1 once SVE is added.

A side-effect of the patch is that we now generate:

        mov     x29, sp

instead of:

        add     x29, sp, 0

in the pr70044.c test.

2018-01-11  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_force_temporary): Assert that
	x exists before using it.
	(aarch64_add_constant_internal): Rename to...
	(aarch64_add_offset_1): ...this.  Replace regnum with separate
	src and dest rtxes.  Handle the case in which they're different,
	including when the offset is zero.  Replace scratchreg with an rtx.
	Use 2 additions if there is no spare register into which we can
	move a 16-bit constant.
	(aarch64_add_constant): Delete.
	(aarch64_add_offset): Replace reg with separate src and dest
	rtxes.  Take a poly_int64 offset instead of a HOST_WIDE_INT.
	Use aarch64_add_offset_1.
	(aarch64_add_sp, aarch64_sub_sp): Take the scratch register as
	an rtx rather than an int.  Take the delta as a poly_int64
	rather than a HOST_WIDE_INT.  Use aarch64_add_offset.
	(aarch64_expand_mov_immediate): Update uses of aarch64_add_offset.
	(aarch64_expand_prologue): Update calls to aarch64_sub_sp,
	aarch64_allocate_and_probe_stack_space and aarch64_add_offset.
	(aarch64_expand_epilogue): Update calls to aarch64_add_offset
	and aarch64_add_sp.
	(aarch64_output_mi_thunk): Use aarch64_add_offset rather than
	aarch64_add_constant.

gcc/testsuite/
	* gcc.target/aarch64/pr70044.c: Allow "mov x29, sp" too.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r256532

In preparation for the switch to NUM_POLY_INT_COEFFS==2.

2018-01-11  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* config/aarch64/aarch64.c (aarch64_reinterpret_float_as_int):
	Use scalar_float_mode.

From-SVN: r256531

This patch replaces GET_MODE_NUNITS in some of the v8.4 support
with equivalent values, in preparation for the switch to
NUM_POLY_INT_COEFFS==2.

2018-01-11  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* config/aarch64/aarch64-simd.md
	(aarch64_fml<f16mac1>l<f16quad>_low<mode>): Avoid GET_MODE_NUNITS.
	(aarch64_fml<f16mac1>l<f16quad>_high<mode>): Likewise.
	(aarch64_fml<f16mac1>l_lane_lowv2sf): Likewise.
	(aarch64_fml<f16mac1>l_lane_highv2sf): Likewise.
	(aarch64_fml<f16mac1>lq_laneq_lowv4sf): Likewise.
	(aarch64_fml<f16mac1>lq_laneq_highv4sf): Likewise.
	(aarch64_fml<f16mac1>l_laneq_lowv2sf): Likewise.
	(aarch64_fml<f16mac1>l_laneq_highv2sf): Likewise.
	(aarch64_fml<f16mac1>lq_lane_lowv4sf): Likewise.
	(aarch64_fml<f16mac1>lq_lane_highv4sf): Likewise.

From-SVN: r256530

2018-01-11  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

	PR target/83514
	* config/arm/arm.c (arm_declare_function_name): Set arch_to_print if
	targ_options->x_arm_arch_string is non NULL.

From-SVN: r256529

2018-01-11  Richard Biener  <rguenther@suse.de>
	Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	PR lto/81968
	libiberty/
	* simple-object-common.h (struct simple_object_functions):
	Change copy_lto_debug_sections callback signature.
	* simple-object-elf.c (SHN_HIRESERVE, SHT_SYMTAB_SHNDX,
	SHF_INFO_LINK): Add defines.
	(simple_object_elf_copy_lto_debug_sections): Instead of
	leaving not to be copied sections empty unnamed SHT_NULL
	remove them from the target section headers and adjust section
	reference everywhere.  Handle SHN_XINDEX in the symbol table
	processing properly.
	* simple-object.c (handle_lto_debug_sections): Change
	interface to return a modified string and handle renaming
	of relocation sections.

Co-Authored-By: Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>

From-SVN: r256528

	* config/aarch64/aarch64.h
	(AARCH64_FL_FOR_ARCH8_4): Add  AARCH64_FL_DOTPROD.

gcc/testsuite/
2018-01-11  Tamar Christina  <tamar.christina@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/vdot-compile-2.c: New.

From-SVN: r256527

The bug reported a particular test di-longlong64-sync-1.c failing when run
on arm-linux-gnueabi with options -mthumb -march=armv5t -O[g,1,2,3] and
-mthumb -march=armv6 -O[g,1,2,3].

The crash was caused because of the explicit VOIDmode argument that is sent
to emit_store_flag_force () and that the emit_store_flag_force () was not
handling the VOIDmode adequately. This patch fixes that.

ChangeLog entries:

*** gcc/ChangeLog ***

2017-01-11  Sudakshina Das  <sudi.das@arm.com>

	PR target/82096
	* expmed.c (emit_store_flag_force): Swap if const op0
	and change VOIDmode to mode of op0.

*** gcc/testsuite/ChangeLog ***

2017-01-11  Sudakshina Das  <sudi.das@arm.com>

	PR target/82096
	* gcc.c-torture/compile/pr82096.c: New test.

From-SVN: r256526

The new opt_mode asserts triggered for replace_reg_with_saved_mem
because it was passing bytes rather than bits to mode_for_size.
Previously we ended up with a BLKmode register instead, but
presumably that didn't matter because this is "only" used for
debug insns.

2018-01-11  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	PR rtl-optimization/83761
	* caller-save.c (replace_reg_with_saved_mem): Pass bits rather
	than bytes to mode_for_size.

From-SVN: r256525

When an object of a type with a specified Default_Value aspect is
declared without an explicit initial value and the default value is
out of range of the objects subtype, the compiler now issues a warning
that Constraint_Error will be raised due to an out-of-range value.

The test below must output a compiler warning as follows:

$ gcc -c -gnatj70 default_warning.adb
default_warning.adb:7:08: warning: value not in range of type
                          "Subint" defined at line 5,
                          "Constraint_Error" will be raised at run
                          time

procedure Default_Warning is

   type Int_With_Default is new Integer with Default_Value => 0;

   subtype Subint is Int_With_Default range 1 .. 100;

   S : Subint;

begin
   null;
end Default_Warning;

2018-01-11  Gary Dismukes  <dismukes@adacore.com>

gcc/ada/

	* exp_ch3.adb (Default_Initialize_Object): Call New_Copy_Tree on the
	result of Get_Simple_Init_Value and pass the source location of the
	object declaration's object_definition.

From-SVN: r256524

The presence of an address clause complicates the build-in-place expansion
because the indicated address must be processed before the indirect call is
generated, including the definition of a local pointer to the object.

The address clause may come from an aspect specification or from an explicit
attribute specification appearing after the object declaration. These two
cases require different processing.

2018-01-11  Ed Schonberg  <schonberg@adacore.com>

gcc/ada/

	* exp_ch6.adb (Make_Build_In_Place_Call_In_Object_Declaration): Handle
	properly object declarations with initializations that are
	build-in-place function calls, when there is an address specification,
	either as an aspect specification or an explicit attribute
	specification clause, for the initialized object.
	* freeze.adb (Check_Address_Clause): Do not remove side-effects from
	initial expressions in the case of a build-in-place call.

gcc/testsuite/

	* gnat.dg/bip_overlay.adb, gnat.dg/bip_overlay.ads: New testcase.

From-SVN: r256523

Frontend only calls Is_Null_Range and Not_Null_Range routines on full views
of types, but backends (for example GNATprove) might call them also on
private types. This patch adapts those routines to transparently retrieve
the full type when called on a private type.

No frontend test, because only external backends are affected.

2018-01-11  Piotr Trojanek  <trojanek@adacore.com>

gcc/ada/

	* sem_eval.adb (Is_Null_Range): Retrieve the full view when called on a
	private (sub)type; refactor to avoid early return statement.
	(Not_Null_Range): Same as above.

From-SVN: r256522

This patch ensures that single concurrent type declarations are marked as Ghost
when they appear within a Ghost region. In addition, the patch verifies that no
concurrent type is declared within a Ghost region and issues an error.

------------
-- Source --
------------

--  types.ads

package Types with Ghost is
   protected Prot_Obj is                                             --  Error
   end Prot_Obj;

   protected type Prot_Typ is                                        --  Error
   end Prot_Typ;

   task Task_Obj;                                                    --  Error

   task type Task_Typ;                                               --  Error
end Types;

----------------------------
-- Compilation and output --
----------------------------

$ gcc -c types.ads
types.ads:2:14: ghost type "Prot_Obj" cannot be concurrent
types.ads:5:19: ghost type "Prot_Typ" cannot be concurrent
types.ads:8:09: ghost type "Task_Obj" cannot be concurrent
types.ads:10:14: ghost type "Task_Typ" cannot be concurrent

2018-01-11  Hristian Kirtchev  <kirtchev@adacore.com>

gcc/ada/

	* freeze.adb (Freeze_Entity): Ensure that a Ghost type is not
	concurrent, nor effectively volatile.
	* ghost.adb (Check_Ghost_Type): New routine.
	* ghost.ads (Check_Ghost_Type): New routine.
	* sem_util.adb (Is_Declaration): Reimplemented. The routine can now
	consider specific subsets of declarations.
	(Is_Declaration_Other_Than_Renaming): Removed. Its functionality is
	replicated by Is_Declaration.
	* sem_util.ads (Is_Declaration): New parameter profile. Update the
	comment on usage.
	(Is_Declaration_Other_Than_Renaming): Removed.

From-SVN: r256521

This patch modifies the analysis of assignment statements to detect an illegal
attempt to alter the value of single protected type Part_Of constituent when
inside a protected function.

2018-01-11  Hristian Kirtchev  <kirtchev@adacore.com>

gcc/ada/

	* sem_ch5.adb (Analyze_Assignment): Assignments to variables that act
	as Part_Of consituents of single protected types are illegal when they
	take place inside a protected function.
	(Diagnose_Non_Variable_Lhs): Use Within_Function to check for an
	enclosing function.
	(Is_Protected_Part_Of_Constituent): New routine.
	(Within_Function): New routine.

gcc/testsuite/

	* gnat.dg/protected_func.adb, gnat.dg/protected_func.ads: New testcase.

From-SVN: r256520

2018-01-11  Arnaud Charlet  <charlet@adacore.com>

gcc/ada/

	Bump copyright notices to 2018.

From-SVN: r256519

2018-01-11  Hristian Kirtchev  <kirtchev@adacore.com>

gcc/ada/

	* binde.adb, par-ch6.adb, par-ch9.adb, sem_ch12.adb, sem_ch13.adb:
	Minor reformatting.

From-SVN: r256518

This patch fixes an issue whereby an expression within an expression
function declaration or completion without proper parenthesization is
incorrectly accepted by the compiler.

2018-01-11  Justin Squirek  <squirek@adacore.com>

gcc/ada/

	* par-ch6.adb (Scan_Body_Or_Expression_Function): Add additional check
	to make sure a given expression function is properly parenthesized.

gcc/testsuite/

	* gnat.dg/expr_func4.adb: New testcase.

From-SVN: r256517

This patch modifies the analysis of subprogram bodies to catch a case where a
pure subprogram body unit depends on non-pure units.

2018-01-11  Hristian Kirtchev  <kirtchev@adacore.com>

gcc/ada/

	* sem_ch6.adb (Analyze_Subprogram_Body_Helper): Check the
	categorization of a subprogram body which does not complete a previous
	declaration.

gcc/testsuite/

	* gnat.dg/pure_subp_body.adb, gnat.dg/pure_subp_body_pkg.ads: New
	testcase.

From-SVN: r256516

This patch updates the detection of illegal with clauses which import private
child packages to properly detect a grandchild of Ada.

------------
-- Source --
------------

--  fake.ads

package Fake is
end Fake;

--  fake-ada.ads

package Fake.Ada is
end Fake.Ada;

--  fake-ada-text_io.ads

package Fake.Ada.Text_IO is
end Fake.Ada.Text_IO;

--  fake-ada-text_io-float_io.ads

private generic
   type Num is digits <>;

package Fake.Ada.Text_IO.Float_IO is
end Fake.Ada.Text_IO.Float_IO;

--  fake-float_io.ads

private generic
   type Num is digits <>;

package Fake.Float_IO is
end Fake.Float_IO;

--  main.ads

with Fake.Ada.Text_IO.Float_IO;
with Fake.Float_IO;

package Main is
end Main;

----------------------------
-- Compilation and output --
----------------------------

$ gcc -c main.ads
main.ads:1:06: unit in with clause is private child unit
main.ads:1:06: current unit must also have parent "Text_IO"
main.ads:2:06: unit in with clause is private child unit
main.ads:2:06: current unit must also have parent "Fake"

2018-01-11  Hristian Kirtchev  <kirtchev@adacore.com>

gcc/ada/

	* sem_ch10.adb (Check_Private_Child_Unit): Ensure that the enclosing
	scope of package Ada is Standard.

From-SVN: r256515

This patch fixes a visibility error in the expression for a dynamic predicate
of a record type, when the expression contains a reference to a subcomponent
of the record given by a selected component whose prefix is the name of the
enclosing component.

Executing

   gnatmake -q -gnata main
   ./main

must yield:

   TGV OK
   Amtrak broken, as usual

----
with Text_IO; use Text_IO;
with Recpred; use Recpred;
procedure Main is
   TGV : Train_Data;
   Amtrak : Train_Data;
begin
  TGV  := (20, (10,10));
  Put_Line ("TGV OK");

  begin
     Amtrak := (30, (40, 40));
  exception
     when Others =>
        Put_Line ("Amtrak broken, as usual");
  end;
end;
----
package Recpred is

   type Train_Position is record
      TTD : Integer;
      VSS : Integer;
   end record;

   type Train_Data is record
      MA             : Integer;
      Front_Position : Train_Position;
   end record
     with Dynamic_Predicate => MA >= Front_Position.TTD;

end Recpred;

2018-01-11  Ed Schonberg  <schonberg@adacore.com>

gcc/ada/

	* sem_ch13.adb (Replace_Type_Ref): Handle properly reference to a
	subcomponent of the current entity when building the body for a dynamic
	predicate function for a record with composite subcomponents.

From-SVN: r256514

This patch modifies the transient scope mechanism to prevent secondary stack
leaks during object initialization. The modifications are as follows:

1) Prior to this change, the secondary stack was never managed within type
initialization procedures, for reasons unknown. It is speculated that the
controlled type model used at that time may have influenced this decision.
The secondary stack is now managed within type initialization procedures
in order to recover the memory once individual components or whole objects
are initialized.

2) A transient scope now delegates the secondary stack management to an
enclosing scope if there is no suitable context to wrap. This ensures that
the requirement to manage the secondary stack is not lost when the scope was
established for that purpose in mind.

3) A previous mechanism which examined the definition of a type (recursively)
to determine whether the type will involve the secondary stack was removed
because a) the mechanism could not detect this need with certainty, and b) the
trigger for secondary stack usage is now moved to the resolution of function
calls, which is always accurate.

------------
-- Source --
------------

--  types.ads

with Ada.Finalization; use Ada.Finalization;

package Types is
   type Ctrl is new Controlled with record
      Id : Integer;
   end record;

   procedure Initialize (Obj : in out Ctrl);

   function Make_Ctrl return Ctrl;
   function Make_Ctrl_From (Obj : Ctrl) return Ctrl;

   type Constr is array (1 .. 3) of Ctrl;
   type Unconstr is array (Integer range <>) of Ctrl;

   function Make_Constr return Constr;
   function Make_Unconstr (Low : Integer; High : Integer) return Unconstr;

   type Rec_1 is new Controlled with record
      Comp : Ctrl := Make_Ctrl;
   end record;

   type Rec_2 is new Controlled with record
      Comp : Ctrl := Make_Ctrl_From (Make_Ctrl);
   end record;

   type Rec_3 is new Controlled with record
      Comp : Constr := Make_Constr;
   end record;

   type Rec_4 is new Controlled with record
      Comp : Unconstr (1 .. 3) := Make_Unconstr (1, 3);
   end record;

   type Rec_5 is record
      Comp : Integer := 1 + Make_Ctrl.Id;
   end record;

   type Rec_6 is record
      Comp : Boolean := (for all X in 1 .. Make_Ctrl.Id =>
                           X = Make_Ctrl.Id);
   end record;
end Types;

--  types.adb

package body Types is
   Id_Gen : Integer := 0;

   procedure Initialize (Obj : in out Ctrl) is
   begin
      Id_Gen := Id_Gen + 1;
      Obj.Id := Id_Gen;
   end Initialize;

   function Make_Constr return Constr is
      Result : constant Constr := (others => Make_Ctrl);
   begin
      return Result;
   end Make_Constr;

   function Make_Ctrl return Ctrl is
      Result : Ctrl;
   begin
      return Result;
   end Make_Ctrl;

   function Make_Ctrl_From (Obj : Ctrl) return Ctrl is
      Result : Ctrl;
   begin
      Result.Id := Obj.Id;
      return Result;
   end Make_Ctrl_From;

   function Make_Unconstr (Low : Integer; High : Integer) return Unconstr is
      Result : constant Unconstr (Low .. High) := (others => Make_Ctrl);
   begin
      return Result;
   end Make_Unconstr;
end Types;

--  maker.ads

generic
   type Obj_Typ is private;
procedure Maker (Count : Positive);

--  maker.adb

procedure Maker (Count : Positive) is
   procedure Create is
      Obj : Obj_Typ;
      pragma Warnings (Off, Obj);
   begin null; end Create;

begin
   for Iter in 1 .. Count loop
      Create;
   end loop;
end Maker;

--  leaks.adb

with Maker;
with Types; use Types;

with Maker;
with Types; use Types;

procedure Leaks is
   procedure Make_1 is new Maker (Rec_1);
   procedure Make_2 is new Maker (Rec_2);
   procedure Make_3 is new Maker (Rec_3);
   procedure Make_4 is new Maker (Rec_4);
   procedure Make_5 is new Maker (Rec_5);
   procedure Make_6 is new Maker (Rec_6);

begin
   Make_1 (5_000);
   Make_2 (5_000);
   Make_3 (5_000);
   Make_4 (5_000);
   Make_5 (5_000);
   Make_6 (5_000);
end Leaks;

----------------------------
-- Compilation and output --
----------------------------

$ gnatmake -q leaks.adb
$ valgrind ./leaks > leaks.txt 2>&1
$ grep -c "still reachable" leaks.txt
0

2018-01-11  Hristian Kirtchev  <kirtchev@adacore.com>

gcc/ada/

	* exp_aggr.adb (Convert_Aggr_In_Object_Decl): Update the call to
	Establish_Transient_Scope.
	(Convert_To_Assignments): Update the call to Establish_Transient_Scope.
	(Expand_Array_Aggregate): Update the call to Establish_Transient_Scope.
	* exp_ch6.adb (Expand_Call_Helper): Update the call to
	Establish_Transient_Scope.
	(Make_Build_In_Place_Call_In_Object_Declaration): Update the call to
	Establish_Transient_Scope.
	* exp_ch7.adb (Establish_Transient_Scope): Restructured. Delegate the
	management of the secondary stack to an enclosing scope if there is no
	suitable construct to wrap, and the transient scope was intended to
	manage the secondary stack.
	(Find_Node_To_Be_Wrapped): Restructured. A case_statement_alternative
	is a valid boundary for a transient expression which comes from the
	statements of the alternative, otherwise alternatives cannot be
	wrapped. Assignments of controlled objects which have controlled
	actions suppressed now stop the traversal as there is no point in
	looking for an enclosing construct. Add several N_xxx_Body choices to
	the termination conditions for completeness.
	* exp_ch7.ads (Establish_Transient_Scope): Update the parameter profile
	and the associated comment on usage.
	* exp_smem.adb (Add_Shared_Var_Lock_Procs): Update the call to
	Establish_Transient_Scope.
	(Add_Write_After): Update the call to Establish_Transient_Scope.
	* sem_res.adb (Check_Initialization_Call): Removed.
	(Resolve_Actuals): Account for additional cases where finalization
	actions are required by utilizing predicate Needs_Finalization rather
	than Is_Controlled.
	(Resolve_Call): Type initialization procedures can now utilize
	transient scopes to manage the secondary stack, thus preventing leaks
	during initialization.  Remove the previous kludgy algorithm which
	attempts to manage the secondary stack at the object creation site.

From-SVN: r256513

2018-01-11  Jerome Lambourg  <lambourg@adacore.com>

gcc/ada/

	* libgnat/g-soliop__qnx.ads: New.
	* adaint.c, adaint.h, cstreams.c, s-oscons-tmplt.c, sysdep.c: Update
	for QNX.

From-SVN: r256512

The syntax rules do not allow null procedures in protected definitions. This
patch fixes a bug that accidentally allowed them.

2018-01-11  Bob Duff  <duff@adacore.com>

gcc/ada/

	* par-ch9.adb (P_Protected_Operation_Declaration_Opt): Give an error if
	a null procedure occurs in a protected definition.

gcc/testsuite/

	* gnat.dg/protected_null.adb: New testcase.

From-SVN: r256511

2018-01-11  Bob Duff  <duff@adacore.com>

gcc/ada/

	* binderr.ads, namet.ads: Minor reformatting.

From-SVN: r256510

2018-01-11  Bob Duff  <duff@adacore.com>

gcc/ada/

	* doc/gnat_ugn/gnat_utility_programs.rst: Improve documentation of
	xml2gnat.

From-SVN: r256509

If the -felab-order.txt switch is given to gnatbind, and there are duplicate
unit names in elab-order.txt, an error will be given.

The following test should get errors:

this (spec) <-- that (body)
error: elab-order.txt:5: duplicate unit name "this (spec)" from line 1
error: elab-order.txt:7: duplicate unit name "that (body)" from line 3
gnatmake: *** bind failed.

Content of elab-order.txt (7 lines):

this%s

that%b

this (spec)

that%b

gnatmake -q -f -g -O0 -gnata that-main.adb -bargs -felab-order.txt

package body That is
end That;
package That is
   pragma Elaborate_Body;
end That;
with This, That;
procedure That.Main is
begin
   null;
end That.Main;
package body This is
end This;
package This is
   pragma Elaborate_Body;
end This;

2018-01-11  Bob Duff  <duff@adacore.com>

gcc/ada/

	* binde.adb (Force_Elab_Order): Give an error if there are duplicate
	unit names.

From-SVN: r256508

An implicit dereference freezes the corresponding designated type. Most
implicit dereferences are made explicit during expansion, but this is not the
case for a dispatching call where the the controlling parameter and the
corresponding controlling argument are access to a tagged type. In that case,
to enforce the rule that an expression function that is a completion freezes
type references within, we must locate controlling arguments of an access type
and freeze explicitly the corresponding designated type.

2018-01-11  Ed Schonberg  <schonberg@adacore.com>

gcc/ada/

	* sem_ch6.adb (Freeze_Expr_Types): If an access value is the
	controlling argument of a dispatching call. freeze the corresponding
	designated type.

gcc/testsuite/

	* gnat.dg/expr_func3.adb, gnat.dg/expr_func3.ads: New testcase.

From-SVN: r256507

2018-01-11  Ben Brosgol  <brosgol@adacore.com>

gcc/ada/

	* doc/Makefile: Add Sphinx option -W to treat warnings as errors.

From-SVN: r256506

2018-01-11  Ben Brosgol  <brosgol@adacore.com>

gcc/ada/

	* doc/gnat_rm/implementation_defined_aspects.rst: Minor type/wording
	corrections.
	* gnat_rm.texi: Regenerate.

From-SVN: r256505

The compiler warns when a generic actual is a fixed-point type, because
arithmetic operations in the instance will use the predefined operations on
it, even if the type has user-defined primitive operations (unless formsl
surprograms for these operations appear in the generic). This patch refines
this warning to exclude the case where the formsal type is private, because
in this case there can be no suspicious arithmetic operastions in the generic
unit.

2018-01-11  Ed Schonberg  <schonberg@adacore.com>

gcc/ada/

	* sem_ch12.adb (Check_Fixed_Point_Type): Do not apply check if the
	formsl type corresponding to the actual fixed point type is private,
	because in this case there can be no suspicious arithmetic operations
	in the generic unless they reference a formal subprogram.  Clarify
	warning.

gcc/testsuite/

	* gnat.dg/fixedpnt2.adb, gnat.dg/fixedpnt2.ads: New testcase.

From-SVN: r256504

exp_util.adb (Remove_Side_Effects): No action done for functions returning class-wide types since it requires...

2018-01-11  Javier Miranda  <miranda@adacore.com>

gcc/ada/

	* exp_util.adb (Remove_Side_Effects): No action done for functions
	returning class-wide types since it requires generating code using
	'reference and the CCG target has no secondary stack.
	* gnat1drv.adb: Disable building static dispatch tables when generating
	C code.

From-SVN: r256503

GNATprove was emitting spurious checks about objects of the File_Type being
uninitialized and there was no easy to fix that (those checks could only be
silenced by pragma Annotate or by hiding File_Type behind as SPARK wrapper).

Now the full view of File_Type is annotated with Default_Initial_Condition
and GNATprove knows that objects of that type are default-initialized. The
default initialization is implicitly defined in the Ada RM (as indeed
there is no procedure that would take an IN OUT parameter of that type).

Semantics of Ada programs shall not be affected by these annotations,
so no frontend test is provided. It only affects GNATprove.

2018-01-11  Piotr Trojanek  <trojanek@adacore.com>

gcc/ada/

	* libgnat/a-direio.ads, libgnat/a-sequio.ads, libgnat/a-ststio.ads,
	libgnat/a-textio.ads, libgnat/a-witeio.ads, libgnat/a-ztexio.ads
	(File_Type): Add Default_Initial_Condition aspect.

From-SVN: r256502