2015-07-07  Tom de Vries  <tom@codesourcery.com>

	* tree-cfg.c (get_virtual_phi): New function.
	* tree-cfg.h (get_virtual_phi): Declare.
	* tree-ssa-loop-manip.c (replace_uses_in_dominated_bbs)
	(rewrite_virtuals_into_loop_closed_ssa): New function.
	* tree-ssa-loop-manip.h (rewrite_virtuals_into_loop_closed_ssa):
	Declare.
	* tree-parloops.c (replace_uses_in_bbs_by): Remove.
	(transform_to_exit_first_loop_alt): Use
	rewrite_virtuals_into_loop_closed_ssa.

From-SVN: r225520

The LWXS instruction is part of the micromips ISA which means it is
valid to generate it for the no-smartmips-lwxs.c testcase.

testsuite/
	* gcc.target/mips/no-smartmips-lwxs.c: Change NOMIPS16 to
	NOCOMPRESSION.

From-SVN: r225519

2015-07-07  Richard Biener  <rguenther@suse.de>

	* fold-const.c (fold_binary_loc): Move
	(X & C2) << C1 -> (X << C1) & (C2 << C1) simplification ...
	* match.pd: ... here.
	Add (X * C1) % C2 -> 0 simplification pattern derived from
	extract_muldiv_1.

	* gcc.dg/vect/vect-over-widen-3-big-array.c: Adjust.

From-SVN: r225517

MIPS: Fix the call-[1,5,6].c tests to allow the jrc instruction to be matched when testing with microMIPS.

When building the call-[1,5,6].c tests for micromips the jrc rather than the
jr instruction is used to call the tail* functions.

testsuite/
	* gcc.target/mips/call-1.c: Allow testcase to match the jrc instruction.
	* gcc.target/mips/call-5.c: Ditto.
	* gcc.target/mips/call-6.c: Ditto.

From-SVN: r225516

PR target/66780
* config/sh/sh.md (symGOT_load): Revert a part of 2015-03-03 change for target/65249.

From-SVN: r225512

2015-07-07  Paulo Matos  <pmatos@broadcom.com>

	* symtab.c (address_matters_1): Fix typo in comment above.
	(can_increase_alignment_p): Likewise.

From-SVN: r225509

2015-07-07  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

	* function.c (free_after_compilation): Clear PROP_cfg in f->curr_properties.
testsuite/
	* gcc.dg/dx-test.c: New test-case.

From-SVN: r225508

gcc/testsuite/ChangeLog:

2015-07-07  Andre Vehreschild  <vehre@gcc.gnu.org>

	PR fortran/66578
	* gfortran.dg/allocate_with_source_9.f08: New test.


gcc/fortran/ChangeLog:

2015-07-07  Mikael Morin  <mikael@gcc.gnu.org>
	    Andre Vehreschild  <vehre@gcc.gnu.org>

	PR fortran/66578
	* trans-array.c (gfc_conv_expr_descriptor): Ensure array descriptor
	is one-based for non-full array refs. Correct the offset when a
	rank_remap occurs.

From-SVN: r225507

2015-07-07  Richard Biener  <rguenther@suse.de>

	* tree-ssa-propagate.c (add_ssa_edge): Dump what edge list we
	add which use to.
	(add_control_edge): Remove excessive vertical space in dumping.
	(process_ssa_edge_worklist): Simulate at most one statement and
	return whether we did.  Do not simulate PHIs if they are in a
	BB not yet simulated.
	(ssa_propagate): Adjust to always drain the BB worklist whenever
	a BB is available there, likewise the VARYING edges list before
	the interesting edge list.

From-SVN: r225504

PR target/52144
* config/arm/elf.h (TARGET_ASM_FILE_START_APP_OFF): Delete.

PR target/52144
* gcc.target/arm/flip-thumb.c: Fix scan.
* gcc.target/arm/attr_thumb.c: Test for all targets. Fix scan.
* gcc.target/arm/attr_arm.c: Test for all targets. Fix scan.
* gcc.target/arm/attr_thumb-static.c: Test for all targets.
Fix return value.

From-SVN: r225503

2015-07-07  Richard Biener  <rguenther@suse.de>

	PR middle-end/66739
	* match.pd: Condition A - B ==/!= 0 -> A ==/!= B on single-use
	A - B.

From-SVN: r225502

From-SVN: r225501

	* pt.c (reduce_template_parm_level): Also build the TYPE_DECL
	for a template template parameter.
	(tsubst_decl) [TEMPLATE_DECL]: Use the TEMPLATE_DECL built
	by reduce_template_parm_level.

From-SVN: r225495

	* pt.c (argument_pack_element_is_expansion_p): A decl pack is an
	expansion.

From-SVN: r225494

	* config/i386/i386.md (insv<mode>): Rename from insv.  Use SWI48
	modes for operands 0 and 3.  Use SImode for operands 2 and 3.
	Copy operand 0 to a temporary if !ext_register_operand.  Remove
	ancient extract_bit_field workaround.
	(insv<mode>_1): Rename from mov<mode>_insv_1.
	(*insvqi): Rename from *movqi_insv_2.
	* config/i386/i386.c (emit_i386_cw_initialization): Update calls
	for renamed insvsi_1.
	(promote_duplicated_reg): Ditto for renamed insv<mode>_1.

From-SVN: r225484

	* config/nvptx/nvptx.c (nvptx_reorg): Remove unused vars.  Fix
	call to nvptx_reorg_subreg.

From-SVN: r225481

From-SVN: r225480

gcc/
	* graphite-blocking.c (HAVE_isl): Include <stddef.h>.
	* graphite-dependencies.c, graphite-interchange.c,
	graphite-isl-ast-to-gimple.c, graphite-optimize-isl.c, graphite-poly.c,
	graphite-scop-detection.c, graphite-sese-to-poly.c, graphite.c:
	Likewise.

From-SVN: r225478

2015-07-06  Marc Glisse  <marc.glisse@inria.fr>

	* match.pd: Remove element_mode inside HONOR_*.
	(~ (-A) -> A - 1, ~ (A - 1) -> -A): Handle complex types.
	(~X | X -> -1, ~X ^ X -> -1): Merge.
	* tree.c (build_each_one_cst): New function.
	* tree.h (build_each_one_cst): Likewise.

From-SVN: r225473

Define __i586__/__pentium__ for -march=iamcu and __tune_iamcu__ for
-mtune=iamcu.

	* config/i386/i386-c.c (ix86_target_macros_internal): Handle
	PROCESSOR_IAMCU.

From-SVN: r225471

2015-07-06  Steve Ellcey  <sellcey@imgtec.com>

	* config.gcc <mips*-*-*>: Add fused-madd.opt.
	* config/mips/mips.opt (mfused-madd): Remove.
	* config/mips/mips.c (mips_rtx_costs): Update cost calculations.
	* config/mips/mips.h (TARGET_MIPS8000): New.
	(ISA_HAS_FP_MADD4_MSUB4): Remove.
	(ISA_HAS_FP_MADDF_MSUBF): Remove.
	(ISA_HAS_FP_MADD3_MSUB3): Remove.
	(ISA_HAS_NMADD4_NMSUB4): Remove.
	(ISA_HAS_NMADD3_NMSUB3): Remove.
	(ISA_HAS_FUSED_MADD4): New.
	(ISA_HAS_UNFUSED_MADD4): New.
	(ISA_HAS_FUSED_MADDF): New.
	(ISA_HAS_FUSED_MADD3): New.
	* config/mips/mips.md: (fma<mode>4) Change from insn to expand.
	(*fma<mode>4_madd3) New.
	(*fma<mode>4_madd4) New.
	(*fma<mode>4_maddf) New.
	(fms<mode>4) New.
	(*fms<mode>4_msub3) New.
	(*fms<mode>4_msub4) New.
	(fnma<mode>4) New.
	(*fnma<mode>4_nmadd3) New.
	(*fnma<mode>4_nmadd4) New.
	(fnms<mode>4) New.
	(*fnms<mode>4_nmsub3) New.
	(*fnms<mode>4_nmsub4) New.
	(*madd4<mode>) Modify to be unfused only.
	(*msub4<mode>) Modify to be unfused only.
	(*nmadd4<mode>) Modify to be unfused only.
	(*nmsub4<mode>) Modify to be unfused only.
	(*madd3<mode>) Remove.
	(*msub3<mode>) Remove.
	(*nmadd3<mode>) Remove.
	(*nmsub3<mode>) Remove.
	(*nmadd3<mode>_fastmath) Remove.
	(*nmsub3<mode>_fastmath) Remove.
	(*nmadd4<mode>_fastmath) Update condition.
	(*nmsub4<mode>_fastmath) Update condition.

From-SVN: r225468

2015-05-05  Jakub Jelinek  <jakub@redhat.com>

	PR target/65956
	* gcc.c-torture/execute/pr65956.c: New test.

From-SVN: r225466

gcc/:
	PR target/65956
	* config/arm/arm.c (arm_needs_doubleword_align): Drop any outer
	alignment attribute, exploring one level down for records and arrays.

gcc/testsuite/:

	* gcc.target/arm/aapcs/align1.c: New.
	* gcc.target/arm/aapcs/align_rec1.c: New.
	* gcc.target/arm/aapcs/align2.c: New.
	* gcc.target/arm/aapcs/align_rec2.c: New.
	* gcc.target/arm/aapcs/align3.c: New.
	* gcc.target/arm/aapcs/align_rec3.c: New.
	* gcc.target/arm/aapcs/align4.c: New.
	* gcc.target/arm/aapcs/align_rec4.c: New.
	* gcc.target/arm/aapcs/align_vararg1.c: New.
	* gcc.target/arm/aapcs/align_vararg2.c: New.

From-SVN: r225465

Default -mtune=/-march= to iamcu for i[34567]86-*-elfiamcu targets.

	* config.gcc (x86_archs): Add iamcu.
	(with_cpu): Default to iamcu for i[34567]86-*-elfiamcu.
	(with_arch): Likewise.
	* doc/invoke.texi: Add iamcu.

From-SVN: r225464

	* config/i386/i386.md (extv<mode>): Rename from extv.  Use SWI24
	modes for operands 0 and 1.  Use SImode for operands 2 and 3.
	Copy operand 1 to a temporary if !ext_register_operand.  Remove
	ancient extract_bit_field workaround.
	(*extv<mode>): Rename from *mov<mode>_extv_1.
	(*extvqi): Rename from *movqi_extv_q.
	(extzv<mode>): Rename from extzv.  Use SWI248 modes for
	operands 0 and 1.  Use SImode for operands 2 and 3. Copy operand 1
	to a temporary if !ext_register_operand.  Remove ancient
	extract_bit_field workaround.
	(*extzv<mode>): Rename from *mov<mode>_extzv_1.
	(*extzvqi): Rename from *movqi_extzv_1.
	(*testqi_ext_3): Remove modes from const_int_operand predicated
	operands.  Add "n" constraint.
	(*btsq, *btrq, *btcq): Remove mode from const_0_to_63 predicated
	operand.  Add "J" constraint.
	(*btsq, *btrq, *btcq peephole2s): Remove mode from
	const_0_to_63 predicated operand.
	(regmode): New insn attribute.
	(*bt<mode>): Use SImode for operand 1.  Change operand 1 predicate
	to nonmemory_operand.  Use regmode insn attribute.
	(*jcc_bt<mode>_1): Convert operand 2 to SImode.
	(*jcc_bt<mode>_mask): Remove mode from operand 3.
	(*jcc_btsi_1, *jcc_btsi_mask_1): Remove patterns.
	(tbm_bextri_<mode>): Remove modes from const_0_to_255 predicated
	operands.  Use "N" constraint instead of "n".

From-SVN: r225463

2015-07-06  Steven G. Kargl  <kargl@gcc.gnu.org>

	* io.c (check_char_variable): New function.
	(match_open_element, match_close_element, match_file_element,
	match_dt_element, match_inquire_element, match_wait_element): Use it.


2015-07-06  Steven G. Kargl  <kargl@gcc.gnu.org>

	* gfortran.dg/iomsg_2.f90: New test.

From-SVN: r225462

        * config/arm/arm.md (movdi): Avoid odd-number ldrd/strd in ARM state.

From-SVN: r225461

IA MCU is based on Intel Pentium ISA without x87 and passing parameters
in registers.  We want to optimize for IA MCU without changing existing
Pentium codegen.  This patch adds PROCESSOR_IAMCU for -march=iamcu,
which is based on -march=pentium with updated cost tables.

gcc/

	PR target/66749
	* config/i386/i386.c (iamcu_cost): New.
	(m_IAMCU): Likewise.
	(initial_ix86_arch_features): Disable X86_ARCH_CMOV for m_IAMCU.
	(processor_target_table): Add an entry for "iamcu".
	(processor_alias_table): Likewise.
	(ix86_issue_rate): Handle PROCESSOR_IAMCU.
	(ix86_adjust_cost): Likewise.
	(ia32_multipass_dfa_lookahead): Likewise.
	* config/i386/i386.h (processor_type): Add PROCESSOR_IAMCU.
	* config/i386/x86-tune.def: Updated for m_IAMCU.

gcc/testsuite/

	PR target/66749
	* gcc.target/i386/pr66749.c: New test.

From-SVN: r225460

2015-07-06  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/66772
	* tree-ssa-ccp.c (ccp_visit_phi_node): Make sure that copy
	values are available in the PHI node BB when there are
	still unexecutable edges.

	* gcc.dg/torture/pr66772-1.c: New testcase.
	* gcc.dg/torture/pr66772-2.c: Likewise.

From-SVN: r225459

    
testsuite/
	* gcc.target/mips/near-far-3.c: Allow the call to near_func to use
	the jals instruction.

From-SVN: r225457

2015-07-06  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/66767
	* tree-vect-loop-manip.c (vect_create_cond_for_align_checks):
	Make sure to build the alignment test on a SSA name without
	final alignment info valid only if the alignment test
	evaluates to true.

From-SVN: r225454

	PR target/66620
	* config/bfin/bfin.c (hwloop_optimize): Create new bb between jump and
	loop start when inserting LSETUP.

From-SVN: r225453

Similar to -mpreferred-stack-boundary=3, -mincoming-stack-boundary=3 is
allowed with -mno-sse in 64-bit mode.

gcc/

	PR target/53383
	* config/i386/i386.c (ix86_option_override_internal): Allow
	-mincoming-stack-boundary=3 for 64-bit if SSE is disabled.

gcc/testsuite/

	PR target/53383
	* gcc.target/i386/pr53383-1.c: New file.
	* gcc.target/i386/pr53383-2.c: Likewise.
	* gcc.target/i386/pr53383-3.c: Likewise.

From-SVN: r225452

	* read-md.c (decimal_string): Rename to ...
	(md_decimal_string): ... this.
	(handle_enum): Reflect this.

From-SVN: r225451

gcc/Changelog:

2015-07-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	PR target/66731
	* config/aarch64/aarch64.md (fnmul<mode>3): Handle -frounding-math.

gcc/testsuite/Changelog:

2015-07-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* gcc.target/aarch64/fnmul-1.c: New.
	* gcc.target/aarch64/fnmul-2.c: New.
	* gcc.target/aarch64/fnmul-3.c: New.
	* gcc.target/aarch64/fnmul-4.c: New.

From-SVN: r225450

2015-07-06  Richard Biener  <rguenther@suse.de>

	PR middle-end/66759
	* match.pd: Add missing constraint of y to REAL_CST in
	REAL_CST - x CMP y to y - CST CMP x simplification.

	* gcc.dg/torture/pr66759.c: New testcase.

From-SVN: r225449

From-SVN: r225448

gcc/testsuite/ChangeLog:

2015-07-06  Andre Vehreschild  <vehre@gmx.de>

	PR fortran/58586
	* gfortran.dg/alloc_comp_class_3.f03: New test.
	* gfortran.dg/alloc_comp_class_4.f03: New test.


gcc/fortran/ChangeLog:

2015-07-06  Andre Vehreschild  <vehre@gmx.de>

	PR fortran/58586
	* resolve.c (resolve_symbol): Non-private functions in modules
	with allocatable or pointer components are marked referenced
	now. Furthermore is the default init especially for those
	components now done in gfc_conf_procedure_call preventing
	duplicate code.
	* trans-decl.c (gfc_generate_function_code): Generate a fake
	result decl for functions returning an object with allocatable
	components and initialize them.
	* trans-expr.c (gfc_conv_procedure_call): For value typed trees
	use the tree without indirect ref. And for non-decl trees
	add a temporary variable to prevent evaluating the tree
	multiple times (prevent multiple function evaluations).
	* trans.h: Made gfc_trans_structure_assign () protoype
	available, which is now needed by trans-decl.c:gfc_generate_
	function_code(), too.

From-SVN: r225447

	PR tree-optimization/66757
	* match.pd: Add missing condition to ~X ^ C -> X ^ ~C.

From-SVN: r225446

	PR libfortran/40267
	* Makefile.am: Remove libgfortranbegin targets.
	* Makefile.in: Regenerate.
	* fmain.c: Remove.

From-SVN: r225445