- 26 Sep, 2019 25 commits
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* function.c (gimplify_parameters): Use build_clobber function. * tree-ssa.c (execute_update_addresses_taken): Likewise. * tree-inline.c (expand_call_inline): Likewise. * tree-sra.c (clobber_subtree): Likewise. * tree-ssa-ccp.c (insert_clobber_before_stack_restore): Likewise. * omp-low.c (lower_rec_simd_input_clauses, lower_rec_input_clauses, lower_omp_single, lower_depend_clauses, lower_omp_taskreg, lower_omp_target): Likewise. * omp-expand.c (expand_omp_for_generic): Likewise. * omp-offload.c (ompdevlow_adjust_simt_enter): Likewise. From-SVN: r276165
Jakub Jelinek committed -
From-SVN: r276164
Alessandro Fanfarillo committed -
[gcc] 2019-09-26 Will Schmidt <will_schmidt@vnet.ibm.com> * config/rs6000/rs6000-builtin.def: (LVSL, LVSR, LVEBX, LVEHX, LVEWX, LVXL, LVXL_V2DF, LVXL_V2DI, LVXL_V4SF, LVXL_V4SI, LVXL_V8HI, LVXL_V16QI, LVX, LVX_V1TI, LVX_V2DF, LVX_V2DI, LVX_V4SF, LVX_V4SI, LVX_V8HI, LVX_V16QI, LVLX, LVLXL, LVRX, LVRXL, LXSDX, LXVD2X_V1TI, LXVD2X_V2DF, LXVD2X_V2DI, LXVDSX, LXVW4X_V4SF, LXVW4X_V4SI, LXVW4X_V8HI, LXVW4X_V16QI, LD_ELEMREV_V1TI, LD_ELEMREV_V2DF, LD_ELEMREV_V2DI, LD_ELEMREV_V4SF, LD_ELEMREV_V4SI, LD_ELEMREV_V8HI, LD_ELEMREV_V16QI): Use the PURE attribute. [testsuite] 2019-09-26 Will Schmidt <will_schmidt@vnet.ibm.com> * gcc.target/powerpc/pure-builtin-redundant-load.c: New. From-SVN: r276163
Will Schmidt committed -
[gcc] 2019-09-26 Will Schmidt <will_schmidt@vnet.ibm.com> * config/rs6000/rs6000-builtin.def: (LVSL, LVSR, LVEBX, LVEHX, LVEWX, LVXL, LVXL_V2DF, LVXL_V2DI, LVXL_V4SF, LVXL_V4SI, LVXL_V8HI, LVXL_V16QI, LVX, LVX_V1TI, LVX_V2DF, LVX_V2DI, LVX_V4SF, LVX_V4SI, LVX_V8HI, LVX_V16QI, LVLX, LVLXL, LVRX, LVRXL, LXSDX, LXVD2X_V1TI, LXVD2X_V2DF, LXVD2X_V2DI, LXVDSX, LXVW4X_V4SF, LXVW4X_V4SI, LXVW4X_V8HI, LXVW4X_V16QI, LD_ELEMREV_V1TI, LD_ELEMREV_V2DF, LD_ELEMREV_V2DI, LD_ELEMREV_V4SF, LD_ELEMREV_V4SI, LD_ELEMREV_V8HI, LD_ELEMREV_V16QI): Use the PURE attribute. [testsuite] 2019-09-26 Will Schmidt <will_schmidt@vnet.ibm.com> * gcc.target/powerpc/pure-builtin-redundant-load.c: New. From-SVN: r276162
Will Schmidt committed -
We can use the mode iterators directly with an @pattern to avoid the need for an expander that was only there to pass the mode through. gcc/ChangeLog: 2019-09-26 Iain Sandoe <iain@sandoe.co.uk> * config/rs6000/darwin.md: Replace the expanders for load_macho_picbase and reload_macho_picbase with use of '@' in their respective define_insns. (nonlocal_goto_receiver): Pass Pmode to gen_reload_macho_picbase. * config/rs6000/rs6000-logue.c (rs6000_emit_prologue): Pass Pmode to gen_load_macho_picbase. * config/rs6000/rs6000.md: Likewise. From-SVN: r276159
Iain Sandoe committed -
2019-09-25 Richard Biener <rguenther@suse.de> PR tree-optimization/91896 * tree-vect-loop.c (vectorizable_reduction): The single def-use cycle optimization cannot apply when there's more than one pattern stmt involved. * gcc.dg/torture/pr91896.c: New testcase. From-SVN: r276158
Richard Biener committed -
tree-vect-loop.c (vect_analyze_loop_operations): Analyze loop-closed PHIs that are vect_internal_def. 2019-09-26 Richard Biener <rguenther@suse.de> * tree-vect-loop.c (vect_analyze_loop_operations): Analyze loop-closed PHIs that are vect_internal_def. (vect_create_epilog_for_reduction): Exit early for nested cycles. Simplify. (vectorizable_lc_phi): New. * tree-vect-stmts.c (vect_analyze_stmt): Call vectorize_lc_phi. (vect_transform_stmt): Likewise. * tree-vectorizer.h (stmt_vec_info_type): Add lc_phi_info_type. (vectorizable_lc_phi): Declare. From-SVN: r276157
Richard Biener committed -
gcc/testsuite/CHangeLog: * gcc.dg/strlenopt-79.c: New test. From-SVN: r276156
Martin Sebor committed -
* include/debug/array (to_array): Define for debug mode. From-SVN: r276155
Jonathan Wakely committed -
* include/bits/stl_pair.h (pair): Add _GLIBCXX20_CONSTEXPR to piecewise construction constructor, assignment operators, and swap. * include/std/tuple (pair::pair(piecewise_construct_t, tuple, tuple)): Add _GLIBCXX20_CONSTEXPR. (pair::pair(tuple, tuple, _Index_tuple, _Index_tuple)): Likewise. * testsuite/20_util/pair/constexpr_assign.cc: New test. * testsuite/20_util/pair/constexpr_swap.cc: New test. From-SVN: r276154
Jonathan Wakely committed -
* include/experimental/internet (operator==, operator<): Fix loop condition to avoid reading past the end of the array. From-SVN: r276153
Jonathan Wakely committed -
* include/std/array: Remove references to profile mode. * include/std/bitset: Likewise. * include/std/deque: Likewise. * include/std/forward_list: Likewise. * include/std/list: Likewise. * include/std/map: Likewise. * include/std/set: Likewise. * include/std/unordered_map: Likewise. * include/std/unordered_set: Likewise. * include/std/vector: Likewise. * testsuite/17_intro/headers/c++1998/profile_mode.cc: New test. * testsuite/17_intro/headers/c++2011/profile_mode.cc: New test. From-SVN: r276152
Jonathan Wakely committed -
From-SVN: r276151
Arnaud Charlet committed -
tree-vect-loop.c (vect_analyze_loop_operations): Also call vectorizable_reduction for vect_double_reduction_def. 2019-09-26 Richard Biener <rguenther@suse.de> * tree-vect-loop.c (vect_analyze_loop_operations): Also call vectorizable_reduction for vect_double_reduction_def. (vect_transform_loop): Likewise. (vect_create_epilog_for_reduction): Move double-reduction PHI creation and preheader argument setting of PHIs ... (vectorizable_reduction): ... here. Also process vect_double_reduction_def PHIs, creating the vectorized PHI nodes, remembering the scalar adjustment computed for the epilogue in STMT_VINFO_REDUC_EPILOGUE_ADJUSTMENT. Remember the original reduction code in STMT_VINFO_REDUC_CODE. * tree-vectorizer.c (vec_info::new_stmt_vec_info): Initialize STMT_VINFO_REDUC_CODE. * tree-vectorizer.h (_stmt_vec_info::reduc_epilogue_adjustment): New. (_stmt_vec_info::reduc_code): Likewise. (STMT_VINFO_REDUC_EPILOGUE_ADJUSTMENT): Likewise. (STMT_VINFO_REDUC_CODE): Likewise. From-SVN: r276150
Richard Biener committed -
2019-09-26 Richard Sandiford <richard.sandiford@arm.com> * MAINTAINERS: Add myself as an aarch64 maintainer. From-SVN: r276149
Richard Sandiford committed -
When -march=native is passed to host_detect_local_cpu to the backend, it overrides all command lines after it. That means $ gcc -march=native -march=armv8-a is treated as $ gcc -march=armv8-a -march=native Prune joined switches with Negative and RejectNegative to allow -march=armv8-a to override previous -march=native on command-line. This is the same fix as was applied for i386 in SVN revision 269164 but for aarch64 and arm. 2019-09-26 Matt Turner <mattst88@gmail.com> PR driver/69471 * config/aarch64/aarch64.opt (march=): Add Negative(march=). (mtune=): Add Negative(mtune=). (mcpu=): Add Negative(mcpu=). * config/arm/arm.opt: Likewise. From-SVN: r276148
Matt Turner committed -
This patch implements some more SIMD32, but these ones have a DImode result+addend. Apart from that there's nothing too exciting about them. Bootstrapped and tested on arm-none-linux-gnueabihf. * config/arm/arm.md (arm_<simd32_op>): New define_insn. * config/arm/arm_acle.h (__smlald, __smlaldx, __smlsld, __smlsldx): Define. * config/arm/arm_acle.h: Define builtins for the above. * config/arm/iterators.md (SIMD32_DIMODE): New int_iterator. (simd32_op): Handle the above. * config/arm/unspecs.md: Define unspecs for the above. * gcc.target/arm/acle/simd32.c: Update test. From-SVN: r276147
Kyrylo Tkachov committed -
This patch is part of a series to implement the SIMD32 ACLE intrinsics [1]. The interesting parts implementation-wise involve adding support for setting and reading the Q bit for saturation and the GE-bits for the packed SIMD instructions. That will come in a later patch. For now, this patch implements the other intrinsics that don't need anything special ; just a mapping from arm_acle.h function to builtin to RTL expander+unspec. I've compressed as many as I could with iterators so that we end up needing only 3 new define_insns. Bootstrapped and tested on arm-none-linux-gnueabihf. [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics * config/arm/arm.md (arm_<simd32_op>): New define_insn. (arm_<sup>xtb16): Likewise. (arm_usada8): Likewise. * config/arm/arm_acle.h (__qadd8, __qsub8, __shadd8, __shsub8, __uhadd8, __uhsub8, __uqadd8, __uqsub8, __qadd16, __qasx, __qsax, __qsub16, __shadd16, __shasx, __shsax, __shsub16, __uhadd16, __uhasx, __uhsax, __uhsub16, __uqadd16, __uqasx, __uqsax, __uqsub16, __sxtab16, __sxtb16, __uxtab16, __uxtb16): Define. * config/arm/arm_acle_builtins.def: Define builtins for the above. * config/arm/unspecs.md: Define unspecs for the above. * config/arm/iterators.md (SIMD32_NOGE_BINOP): New int_iterator. (USXTB16): Likewise. (simd32_op): New int_attribute. (sup): Handle UNSPEC_SXTB16, UNSPEC_UXTB16. * doc/sourcebuild.exp (arm_simd32_ok): Document. * lib/target-supports.exp (check_effective_target_arm_simd32_ok_nocache): New procedure. (check_effective_target_arm_simd32_ok): Likewise. (add_options_for_arm_simd32): Likewise. * gcc.target/arm/acle/simd32.c: New test. From-SVN: r276146
Kyrylo Tkachov committed -
My recent assemble_real patch (r275873) meant that we now output negative FP16 constants in the same way as we'd output an integer subreg of them. This patch updates gcc.target/arm/fp16-* accordingly. 2019-09-26 Richard Sandiford <richard.sandiford@arm.com> gcc/testsuite/ * gcc.target/arm/fp16-compile-alt-3.c: Expect (__fp16) -2.0 to be written as a negative short rather than a positive one. * gcc.target/arm/fp16-compile-ieee-3.c: Likewise. From-SVN: r276145
Richard Sandiford committed -
2019-09-26 Martin Jambor <mjambor@suse.cz> * ipa-sra.c (verify_splitting_accesses): Fix quoting in a call to internal_error. From-SVN: r276144
Martin Jambor committed -
2019-09-26 Martin Jambor <mjambor@suse.cz> * ipa-sra.c (process_scan_results): Fix continue condition. From-SVN: r276143
Martin Jambor committed -
* MAINTAINERS: Add myself as aarch64 maintainer. From-SVN: r276142
Kyrylo Tkachov committed -
2019-09-26 Martin Liska <mliska@suse.cz> PR tree-optimization/91885 * tree-vectorizer.c (try_vectorize_loop_1): Add TODO_update_ssa_only_virtuals similarly to what slp pass does. 2019-09-26 Martin Liska <mliska@suse.cz> PR tree-optimization/91885 * gcc.dg/pr91885.c: New test. From-SVN: r276141
Martin Liska committed -
The PLUS handling in aarch64_rtx_costs only checked for nonnegative constants, meaning that simple immediate subtractions like: (set (reg R1) (plus (reg R2) (const_int -8))) had a cost of two instructions. 2019-09-26 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Use aarch64_plus_immediate rather than aarch64_uimm12_shift to test for valid PLUS immediates. From-SVN: r276140
Richard Sandiford committed -
From-SVN: r276139
GCC Administrator committed
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- 25 Sep, 2019 14 commits
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* config.in, configure: Re-rebuild with stock autoconf 2.69, not the ubuntu modified 2.69. From-SVN: r276135
Richard Henderson committed -
PR target/91833 * config/aarch64/lse-init.c: Include auto-target.h. Disable initialization if !HAVE_SYS_AUXV_H. * configure.ac (AC_CHECK_HEADERS): Add sys/auxv.h. * config.in, configure: Rebuild. From-SVN: r276134
Richard Henderson committed -
PR target/91834 * config/aarch64/lse.S (LDNM): Ensure STXR output does not overlap the inputs. From-SVN: r276133
Richard Henderson committed -
gcc/fortran/ChangeLog: PR fortran/91426 * error.c (curr_diagnostic): New static variable. (gfc_report_diagnostic): New static function. (gfc_warning): Replace call to diagnostic_report_diagnostic with call to gfc_report_diagnostic. (gfc_format_decoder): Colorize the text of %L and %C to match the colorization used by diagnostic_show_locus. (gfc_warning_now_at): Replace call to diagnostic_report_diagnostic with call to gfc_report_diagnostic. (gfc_warning_now): Likewise. (gfc_warning_internal): Likewise. (gfc_error_now): Likewise. (gfc_fatal_error): Likewise. (gfc_error_opt): Likewise. (gfc_internal_error): Likewise. From-SVN: r276132
David Malcolm committed -
Hi, Martin and his clang warnings discovered that I forgot to remove a static inline function and a variable when ripping out the old IPA-SRA from tree-sra.c and both are now unused. Thus I am doing that now with the patch below which I will commit as obvious (after including it in a round of a bootstrap and testing on an x86_64-linux). Thanks, Martin 2019-09-25 Martin Jambor <mjambor@suse.cz> * tree-sra.c (no_accesses_p): Remove. (no_accesses_representant): Likewise. From-SVN: r276128
Martin Jambor committed -
* call.c (convert_like_real): Use similar_type_p in an assert. * g++.dg/conversion/packed1.C: New test. From-SVN: r276127
Marek Polacek committed -
We're somewhat inconsistent in arm_neon.h when it comes to using the implementation namespace for local identifiers. This means things like: #define hash_abcd 0 #define hash_e 1 #define wk 2 #include "arm_neon.h" uint32x4_t foo (uint32x4_t a, uint32_t b, uint32x4_t c) { return vsha1cq_u32 (a, b, c); } don't compile. This patch fixes these issues throughout the whole of arm_neon.h Bootstrapped and tested on aarch64-none-linux-gnu. The advsimd-intrinsics.exp tests pass just fine. From-SVN: r276125
Kyrylo Tkachov committed -
2019-09-25 Richard Biener <rguenther@suse.de> PR tree-optimization/91896 * tree-vect-loop.c (vectorizable_reduction): The single def-use cycle optimization cannot apply when there's more than one pattern stmt involved. * gcc.dg/torture/pr91896.c: New testcase. From-SVN: r276123
Richard Biener committed -
The DCache clean & ICache invalidation requirements for instructions to be data coherence are discoverable through new fields in CTR_EL0. Let's support the two bits if they are enabled, the CPU core will not execute the unnecessary DCache clean or Icache Invalidation instructions. 2019-09-25 Shaokun Zhang <zhangshaokun@hisilicon.com> * config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Add support for CTR_EL0.IDC and CTR_EL0.DIC. From-SVN: r276122
Shaokun Zhang committed -
* include/bits/regex.h (basic_regex::assign(const C*, size_t, flag_type)): Add default argument (LWG 3296). * testsuite/28_regex/basic_regex/assign/char/lwg3296.cc: New test. * testsuite/28_regex/basic_regex/assign/wchar_t/lwg3296.cc: New test. From-SVN: r276121
Jonathan Wakely committed -
2019-09-25 Martin Liska <mliska@suse.cz> * gcc.target/s390/pr91014.c: Move to ... * gcc.dg/pr91014.c: ... this. From-SVN: r276120
Martin Liska committed -
/cp 2019-09-25 Paolo Carlini <paolo.carlini@oracle.com> * name-lookup.c (check_extern_c_conflict): Use DECL_SOURCE_LOCATION. (check_local_shadow): Use it in three additional places. /testsuite 2019-09-25 Paolo Carlini <paolo.carlini@oracle.com> * g++.dg/diagnostic/redeclaration-1.C: New. * g++.dg/lookup/extern-c-hidden.C: Test location(s) too. * g++.dg/lookup/extern-c-redecl.C: Likewise. * g++.dg/lookup/extern-c-redecl6.C: Likewise. * g++.old-deja/g++.other/using9.C: Likewise. From-SVN: r276119
Paolo Carlini committed -
The break here was skipping over the code that sets EXPR_LOCATION on the call expressions, for no good reason. * parser.c (cp_parser_postfix_expression): Do set location of dependent member call. From-SVN: r276112
Jason Merrill committed -
From-SVN: r276111
GCC Administrator committed
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- 24 Sep, 2019 1 commit
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This switches the picbase load and reload patterns to use the 'P' mode iterator instead of writing an SI and DI pattern for each. gcc/ChangeLog: 2019-09-24 Iain Sandoe <iain@sandoe.co.uk> * config/rs6000/rs6000.md (load_macho_picbase_<mode>): New, using the 'P' mode iterator, replacing the (removed) SI and DI variants. (reload_macho_picbase_<mode>): Likewise. From-SVN: r276107
Iain Sandoe committed
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