* include/bits/hashtable_policy.h (_Hashtable_ebo_helper::_S_get):
	Replace with _M_get non-static member function.
	(_Hashtable_ebo_helper::_S_cget): Replace with _M_cget non-static
	member function.
	(_Hash_code_base, _Local_iterator_base, _Hashtable_base):
	(_Hashtable_alloc): Adjust to use non-static members of EBO helper.

From-SVN: r271290

2019-05-16  Martin Liska  <mliska@suse.cz>

	PR lto/90500
	* multiple_target.c (expand_target_clones): Do not allow
	target_clones being used with a symbol that is an alias.
2019-05-16  Martin Liska  <mliska@suse.cz>

	PR lto/90500
	* gcc.target/i386/pr90500-1.c: New test.
	* gcc.target/i386/pr90500-2.c: New test.

From-SVN: r271289

2019-05-16  Vladislav Ivanishin  <vlad@ispras.ru>

	PR tree-optimization/90394
	* tree-ssa-uninit.c (is_pred_expr_subset_of): Potentially give false
	positives rather than ICE for cases where (code2 == NE_EXPR
	&& code1 == BIT_AND_EXPR).

testsuite/
	* gcc.dg/uninit-pr90394-1-gimple.c: New test.
	* gcc.dg/uninit-pr90394.c: New test.

From-SVN: r271287

The const accessors are OK (and arguably more correct) for most callers
to use. The _M_swap functions that use the non-const overloads can just
directly use the _S_get members of the EBO helpers.

	* include/bits/hashtable_policy.h (_Hash_code_base::_M_swap): Use
	_S_get accessors for members in EBO helpers.
	(_Hash_code_base::_M_extract(), _Hash_code_base::_M_ranged_hash())
	(_Hash_code_base::_M_h1(), _Hash_code_base::_M_h2()): Remove non-const
	overloads.
	(_Hashtable_base::_M_swap): Use _S_get accessors for members in EBO
	helpers.
	(_Hashtable_base::_M_eq()): Remove non-const overload.

From-SVN: r271286

	PR fortran/90329
	* tree-core.h (struct tree_decl_common): Document
	decl_nonshareable_flag for PARM_DECLs.
	* tree.h (DECL_HIDDEN_STRING_LENGTH): Define.
	* calls.c (expand_call): Don't try tail call if caller
	has any DECL_HIDDEN_STRING_LENGTH PARM_DECLs that are or might be
	passed on the stack and callee needs to pass any arguments on the
	stack.
	* tree-streamer-in.c (unpack_ts_decl_common_value_fields): Use
	else if instead of series of mutually exclusive ifs.  Handle
	DECL_HIDDEN_STRING_LENGTH for PARM_DECLs.
	* tree-streamer-out.c (pack_ts_decl_common_value_fields): Likewise.

	* trans-decl.c (create_function_arglist): Set
	DECL_HIDDEN_STRING_LENGTH on hidden string length PARM_DECLs if
	len is constant.

From-SVN: r271285

From-SVN: r271284

2019-05-16  Richard Biener  <rguenther@suse.de>

	PR testsuite/90502
	* gcc.dg/tree-ssa/vector-6.c: Adjust for half of the
	transforms happening earlier now.

From-SVN: r271283

In some cases the test using setssbsy was not enough to
detemine support for the CET insns.  Adding -fcf-protection
explicitly causes other insns to be emitted (e.g. endbr32/64)
which are a more complete check.

2019-05-16  Iain Sandoe  <iain@sandoe.co.uk>

	* lib/target-supports.exp (check_effective_target_cet): Add the
	-fcf-protection flag to the build conditions.

From-SVN: r271282

	PR tree-optimization/90106
	* tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds): Add
	new parameter as new internal function call, also move it to new
	basic block.
	(use_internal_fn): Pass internal function call to
	shrink_wrap_one_built_in_call_with_conds.

	gcc/testsuite
	* gcc.dg/cdce1.c: Check tailcall code generation after cdce pass.
	* gcc.dg/cdce2.c: Likewise.

From-SVN: r271281

Account for Cortex-M3 Errata 602117.  The -mfix-cortex-m3-ldrd option is
enabled by default, if -mcpu=cortex-m3 is used.

gcc/

	* config/arm/t-rtems: Replace ARMv7-M multilibs with Cortex-M
	multilibs.

From-SVN: r271280

2019-05-16  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/90424
	* tree-ssa.c (non_rewritable_lvalue_p): Handle inserts from
	aligned subvectors.
	(execute_update_addresses_taken): Likewise.
	* tree-cfg.c (verify_gimple_assign_ternary): Likewise.

	* g++.target/i386/pr90424-1.C: New testcase.
	* g++.target/i386/pr90424-2.C: Likewise.

From-SVN: r271279

2019-05-16  Richard Biener  <rguenther@suse.de>

	c/
	* gimple-parser.c (c_parser_gimple_statement): Handle __BIT_INSERT.
	(c_parser_gimple_unary_expression): Likewise.

	* gimple-pretty-print.c (dump_ternary_rhs): Dump BIT_INSERT_EXPR
	as __BIT_INSERT with -gimple.

	* gcc.dg/gimplefe-40.c: Amend again.

From-SVN: r271278

2019-05-16  Jun Ma  <junma@linux.alibaba.com>

	* MAINTAINERS (Write After Approval): Add myself.

From-SVN: r271277

    
    If an interface does not escape, it doesn't need a heap
    allocation to hold the data (for non-direct interface type).
    This CL improves the escape analysis to track interface
    conversions, and reduces these allocations.
    
    Implicit interface conversions were mostly added late in the
    compilation pipeline, after the escape analysis. For the escape
    analysis to see them, we move the introduction of these
    conversions earlier, right before the escape analysis.
    
    Now that the compiler can generate interface conversions inlined,
    gcc/testsuite/go.test/test/nilptr2.go needs to be adjusted as in
    golang.org/cl/176579, so the use function does an actual use.
    
    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/176459

	* go.test/test/nilptr2.go: Change use function to actually do
	something.

From-SVN: r271276

From-SVN: r271275

	PR middle-end/90478
	* gcc.dg/tree-ssa/pr90478.c: Add empty dg-options.  Use long long type
	instead of long.

From-SVN: r271271

	* omp-low.c (lower_rec_input_clauses): For if (0) or simdlen (1) set
	max_vf to 1.
	* omp-expand.c (expand_omp_simd): For if (0) or simdlen (1) clear
	safelen_int and set loop->dont_vectorize.

	* c-c++-common/gomp/simd8.c: New test.

From-SVN: r271270

	PR debug/90197
	* cp-gimplify.c (genericize_cp_loop): Emit a DEBUG_BEGIN_STMT
	before the condition (or if missing or constant non-zero at the end
	of the loop.  Emit a DEBUG_BEGIN_STMT before the increment expression
	if any.  Don't call protected_set_expr_location on incr if it already
	has a location.

From-SVN: r271269

	* include/std/variant (visit, visit<R>): Qualify calls to __do_visit.

From-SVN: r271268

	* class.c (check_field_decls): Initialize booleans directly.  A union
	is literal if at least one of its non-static data members is of
	non-volatile literal type.

	* g++.dg/cpp0x/literal-type1.C: New test.

From-SVN: r271267

C preprocessor definitions should not be translated.

2019-05-15  Janne Blomqvist  <jb@gcc.gnu.org>

        * parse.c (gfc_parse_file): Remove translation string markers.

From-SVN: r271261

As of Fortran 2018 it's allowed to open the same file on multiple
units.

libgfortran/ChangeLog:

2019-05-15  Janne Blomqvist  <jb@gcc.gnu.org>

	PR fortran/90461
        * io/open.c (new_unit): Don't check if the file is already open
	for F2018.

testsuite/ChangeLog:

2019-05-15  Janne Blomqvist  <jb@gcc.gnu.org>

	PR fortran/90461
        * gfortran.dg/open_errors_2.f90: Add -std=f2008, adjust line number.
	* gfortran.dg/open_errors_3.f90: New test.

From-SVN: r271260

	* config/i386/i386-expand.c (ix86_split_idivmod): Rename
	signed_p argument to unsigned_p.  Update all uses for changed polarity.
	* config/i386/i386.md (u_bool): Handle DIV and UDIV RTXes.
	(divmod splitters): Use u_bool macro in the call to ix86_split_idivmod.

From-SVN: r271259

2019-05-15  Paolo Carlini  <paolo.carlini@oracle.com>

	* cp-tree.h (REFERENCE_VLA_OK): Remove.
	* lambda.c (build_capture_proxy): Remove use of the above.

From-SVN: r271258

Test MMX intrinsics with -msse2 in 32-bit mode and -msse2 -mno-mmx in
64-bit mode.

	PR target/89021
	* gcc.target/i386/mmx-vals.h: New file.
	* gcc.target/i386/sse2-mmx-2.c: Likewise.
	* gcc.target/i386/sse2-mmx-3.c: Likewise.
	* gcc.target/i386/sse2-mmx-4.c: Likewise.
	* gcc.target/i386/sse2-mmx-5.c: Likewise.
	* gcc.target/i386/sse2-mmx-6.c: Likewise.
	* gcc.target/i386/sse2-mmx-7.c: Likewise.
	* gcc.target/i386/sse2-mmx-8.c: Likewise.
	* gcc.target/i386/sse2-mmx-9.c: Likewise.
	* gcc.target/i386/sse2-mmx-10.c: Likewise.
	* gcc.target/i386/sse2-mmx-11.c: Likewise.
	* gcc.target/i386/sse2-mmx-12.c: Likewise.
	* gcc.target/i386/sse2-mmx-13.c: Likewise.
	* gcc.target/i386/sse2-mmx-14.c: Likewise.
	* gcc.target/i386/sse2-mmx-15.c: Likewise.
	* gcc.target/i386/sse2-mmx-16.c: Likewise.
	* gcc.target/i386/sse2-mmx-17.c: Likewise.
	* gcc.target/i386/sse2-mmx-18a.c: Likewise.
	* gcc.target/i386/sse2-mmx-18b.c: Likewise.
	* gcc.target/i386/sse2-mmx-18c.c: Likewise.
	* gcc.target/i386/sse2-mmx-19a.c: Likewise.
	* gcc.target/i386/sse2-mmx-18b.c: Likewise.
	* gcc.target/i386/sse2-mmx-19c.c: Likewise.
	* gcc.target/i386/sse2-mmx-19d.c: Likewise.
	* gcc.target/i386/sse2-mmx-19e.c: Likewise.
	* gcc.target/i386/sse2-mmx-20.c: Likewise.
	* gcc.target/i386/sse2-mmx-21.c: Likewise.
	* gcc.target/i386/sse2-mmx-22.c: Likewise.
	* gcc.target/i386/sse2-mmx-cvtpi2ps.c: Likewise.
	* gcc.target/i386/sse2-mmx-cvtps2pi.c: Likewise.
	* gcc.target/i386/sse2-mmx-cvttps2pi.c: Likewise.
	* gcc.target/i386/sse2-mmx-maskmovq.c: Likewise.
	* gcc.target/i386/sse2-mmx-packssdw.c: Likewise.
	* gcc.target/i386/sse2-mmx-packsswb.c: Likewise.
	* gcc.target/i386/sse2-mmx-packuswb.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddb.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddd.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddq.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddsb.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddsw.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddusb.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddusw.c: Likewise.
	* gcc.target/i386/sse2-mmx-paddw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pand.c: Likewise.
	* gcc.target/i386/sse2-mmx-pandn.c: Likewise.
	* gcc.target/i386/sse2-mmx-pavgb.c: Likewise.
	* gcc.target/i386/sse2-mmx-pavgw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpeqb.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpeqd.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpeqw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpgtb.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpgtd.c: Likewise.
	* gcc.target/i386/sse2-mmx-pcmpgtw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pextrw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pinsrw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmaddwd.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmaxsw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmaxub.c: Likewise.
	* gcc.target/i386/sse2-mmx-pminsw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pminub.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmovmskb.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmulhuw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmulhw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmullw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pmuludq.c: Likewise.
	* gcc.target/i386/sse2-mmx-por.c: Likewise.
	* gcc.target/i386/sse2-mmx-psadbw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pshufw.c: Likewise.
	* gcc.target/i386/sse2-mmx-pslld.c: Likewise.
	* gcc.target/i386/sse2-mmx-pslldi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psllq.c: Likewise.
	* gcc.target/i386/sse2-mmx-psllqi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psllw.c: Likewise.
	* gcc.target/i386/sse2-mmx-psllwi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrad.c: Likewise.
	* gcc.target/i386/sse2-mmx-psradi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psraw.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrawi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrld.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrldi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrlq.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrlqi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrlw.c: Likewise.
	* gcc.target/i386/sse2-mmx-psrlwi.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubb.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubd.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubq.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubusb.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubusw.c: Likewise.
	* gcc.target/i386/sse2-mmx-psubw.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpckhbw.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpckhdq.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpckhwd.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpcklbw.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpckldq.c: Likewise.
	* gcc.target/i386/sse2-mmx-punpcklwd.c: Likewise.
	* gcc.target/i386/sse2-mmx-pxor.c: Likewise.

From-SVN: r271254

This patch enables TM MMX intrinsics with SSE2 when MMX is disabled.

	PR target/89021
	* config/i386/i386-builtins.c (bdesc_tm): Enable MMX intrinsics
	with SSE2.

From-SVN: r271253

Allow MMX intrinsic emulation with SSE/SSE2/SSSE3.  Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.

For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.

gcc/

	PR target/89021
	* config/i386/i386-builtin.def: Enable MMX intrinsics with
	SSE/SSE2/SSSE3.
	* config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins):
	Likewise.
	* config/i386/i386-expand.c (ix86_expand_builtin): Allow
	SSE/SSE2/SSSE3 to emulate MMX intrinsics with TARGET_MMX_WITH_SSE.
	* config/i386/mmintrin.h: Only require SSE2 if __MMX_WITH_SSE__
	is defined.

gcc/testsuite/

	PR target/89021
	* gcc.target/i386/pr82483-1.c: Error only on ia32.
	* gcc.target/i386/pr82483-2.c: Likewise.

From-SVN: r271252

	PR target/89021
	* config/i386/mmx.md (*vec_dupv2sf): Changed to
	define_insn_and_split to support SSE emulation.
	(*vec_extractv2sf_0): Likewise.
	(*vec_extractv2sf_1): Likewise.
	(*vec_extractv2si_0): Likewise.
	(*vec_extractv2si_1): Likewise.
	(*vec_extractv2si_zext_mem): Likewise.
	(vec_setv2sf): Also allow TARGET_MMX_WITH_SSE.
	(vec_extractv2sf_1 splitter): Likewise.
	(vec_extractv2sfsf): Likewise.
	(vec_setv2si): Likewise.
	(vec_extractv2si_1 splitter): Likewise.
	(vec_extractv2sisi): Likewise.
	(vec_setv4hi): Likewise.
	(vec_extractv4hihi): Likewise.
	(vec_setv8qi): Likewise.
	(vec_extractv8qiqi): Likewise.
	(vec_extractv2sfsf): Also allow TARGET_MMX_WITH_SSE.  Pass
	TARGET_MMX_WITH_SSE ix86_expand_vector_extract.
	(vec_extractv2sisi): Likewise.
	(vec_extractv4hihi): Likewise.
	(vec_extractv8qiqi): Likewise.
	(vec_initv2sfsf): Also allow TARGET_MMX_WITH_SSE.  Pass
	TARGET_MMX_WITH_SSE to ix86_expand_vector_init.
	(vec_initv2sisi): Likewise.
	(vec_initv4hihi): Likewise.
	(vec_initv8qiqi): Likewise.
	(vec_setv2si): Also allow TARGET_MMX_WITH_SSE.  Pass
	TARGET_MMX_WITH_SSE to ix86_expand_vector_set.
	(vec_setv4hi): Likewise.
	(vec_setv8qi): Likewise.

From-SVN: r271251

	PR target/89021
	* config/i386/mmx.md (MMXMODE:mov<mode>): Also allow
	TARGET_MMX_WITH_SSE.
	(MMXMODE:*mov<mode>_internal): Likewise.
	(MMXMODE:movmisalign<mode>): Likewise.

From-SVN: r271250

2019-05-15  Uroš Bizjak  <ubizjak@gmail.com>

	PR target/89021
	* config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute.
	* config/i386/sse.md (sse2_cvtpi2pd): Ditto.
	(sse2_cvtpd2pi): Ditto.
	(sse2_cvttpd2pi): Ditto.
	(*vec_concatv2sf_sse4_1): Ditto.
	(*vec_concatv2sf_sse): Ditto.
	(*vec_concatv2si_sse4_1): Ditto.
	(*vec_concatv2si): Ditto.
	(*vec_concatv4si_0): Ditto.
	(*vec_concatv2di_0): Ditto.

From-SVN: r271249

Emulate MMX abs<mode>2 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/sse.md (abs<mode>2): Add SSE emulation.

From-SVN: r271248

Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq.  Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_palignrdi): Changed to
	define_insn_and_split to support SSE emulation.

From-SVN: r271247

Emulate MMX ssse3_psign<mode>3 with SSE.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_psign<mode>3): Add SSE emulation.

From-SVN: r271246

Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte.  Only SSE register source operand is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_pshufbv8qi3): Changed to
	define_insn_and_split.  Also allow TARGET_MMX_WITH_SSE.  Add
	SSE emulation.

From-SVN: r271245

Emulate MMX ssse3_pmulhrswv4hi3 with SSE.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_pmulhrswv4hi3): Require TARGET_MMX
	or TARGET_MMX_WITH_SSE.
	(*ssse3_pmulhrswv4hi3): Add SSE emulation.

From-SVN: r271244

Emulate MMX ssse3_pmaddubsw with SSE.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.

From-SVN: r271243

Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>dv2si3):
	Changed to define_insn_and_split to support SSE emulation.

From-SVN: r271242

Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3):
	Changed to define_insn_and_split to support SSE emulation.

From-SVN: r271241

With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP
without MMX.

	PR target/89021
	* config/i386/mmx.md (mmx_<emms>): Renamed to ...
	(*mmx_<emms>): This.
	(mmx_<emms>): New expander.

From-SVN: r271240

Emulate MMX umulv1siv1di3 with SSE2.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
	support.
	(*sse2_umulv1siv1di3): Add SSE2 emulation.

From-SVN: r271239