for  gcc/c-family/ChangeLog

	PR debug/83527
	PR debug/83419
	* c-semantics.c (only_debug_stmts_after_p): New.
	(pop_stmt_list): Clear side effects in debug-only stmt list.
	Check for single nondebug stmt followed by debug stmts only.

for  gcc/testsuite/ChangeLog

	PR debug/83527
	PR debug/83419
	* gcc.dg/pr83527.c: New.

From-SVN: r255966

From-SVN: r255965

gcc/testsuite/ChangeLog

	* c-c++-common/Warray-bounds-3.c: Adjust dg-warning grep pattern.

From-SVN: r255962

	PR middle-end/83487
	* config/i386/i386.c (ix86_function_arg_boundary): Return
	PARM_BOUNDARY for TYPE_EMPTY_P types.

	* gcc.c-torture/compile/pr83487.c: New test.
	* gcc.dg/compat/pr83487-1.h: New file.
	* gcc.dg/compat/pr83487-1_main.c: New test.
	* gcc.dg/compat/pr83487-1_x.c: New file.
	* gcc.dg/compat/pr83487-1_y.c: New file.
	* gcc.dg/compat/pr83487-2_main.c: New test.
	* gcc.dg/compat/pr83487-2_x.c: New file.
	* gcc.dg/compat/pr83487-2_y.c: New file.
	* g++.dg/abi/pr83487.C: New test.
	* g++.dg/compat/abi/pr83487-1_main.C: New test.
	* g++.dg/compat/abi/pr83487-1_x.C: New file.
	* g++.dg/compat/abi/pr83487-1_y.C: New file.
	* g++.dg/compat/abi/pr83487-2_main.C: New test.
	* g++.dg/compat/abi/pr83487-2_x.C: New file.
	* g++.dg/compat/abi/pr83487-2_y.C: New file.

From-SVN: r255961

	PR c/83448
	* gimple-ssa-sprintf.c (maybe_warn): Don't call set_caret_index
	if navail is >= dir.len.

	* gcc.c-torture/compile/pr83448.c: New test.
	* gcc.dg/tree-ssa/builtin-snprintf-warn-4.c: New test.

From-SVN: r255960

From-SVN: r255959

	* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Variable>: Always take
	into account the Esize if it is known.

From-SVN: r255958

2017-12-21  Steve Ellcey  <sellcey@cavium.com>

	* config/aarch64/t-aarch64-linux (MULTILIB_OSDIRNAMES): Fix
	triplet for ilp32.

From-SVN: r255957

From-SVN: r255955

re PR rtl-optimization/80747 (gcc.dg/tree-ssa/tailrecursion-4.c fails with ICE when compiled with options "-fprofile-use -freorder-blocks-and-partition")

	PR rtl-optimization/80747
	PR rtl-optimization/83512
	* cfgrtl.c (force_nonfallthru_and_redirect): When splitting
	succ edge from ENTRY, copy partition from e->dest to the newly
	created bb.
	* bb-reorder.c (reorder_basic_blocks_simple): If last_tail is
	ENTRY, use BB_PARTITION of its successor block as current_partition.
	Don't copy partition when splitting succ edge from ENTRY.

	* gcc.dg/pr80747.c: New test.
	* gcc.dg/pr83512.c: New test.

From-SVN: r255954

re PR tree-optimization/83523 (ICE: verify_gimple failed (error: statement marked for throw, but doesn't))

	PR tree-optimization/83523
	* tree-ssa-math-opts.c (is_widening_mult_p): Return false if
	for INTEGER_TYPE TYPE_OVERFLOW_TRAPS.
	(convert_mult_to_fma): Likewise.

	* g++.dg/tree-ssa/pr83523.C: New test.

From-SVN: r255953

re PR tree-optimization/83521 (ICE: verify_gimple failed (error: invalid operand in unary operation))

	PR tree-optimization/83521
	* tree-ssa-phiopt.c (factor_out_conditional_conversion): Use
	gimple_build_assign without code on result of
	fold_build1 (VIEW_CONVERT_EXPR, ...), as it might not create
	a VIEW_CONVERT_EXPR.

	* gcc.dg/pr83521.c: New test.

From-SVN: r255952

2017-12-21  Andrew Pinski  <apinski@cavium.com>
	    Steve Ellcey  <sellcey@cavium.com>

	* config/aarch64/t-aarch64-linux (MULTILIB_OSDIRNAMES): Handle
	multi-arch for ilp32.

Co-Authored-By: Steve Ellcey <sellcey@cavium.com>

From-SVN: r255951

https://gcc.gnu.org/ml/gcc-patches/2017-12/msg01432.html
	PR c++/83406
	* parser.c (cp_parser_lambda_body): Remove obsolete
	single-return-statement handling.

	PR c++/83406
	* g++.dg/cpp0x/lambda/lambda-ice15.C: Adjust error.
	* g++.dg/cpp1y/pr83406.C: New.

From-SVN: r255950

re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv)

	PR target/83467
	* config/i386/i386.md (*ashl<mode>3_mask): Add operand
	constraints to operand 2.
	(*ashl<mode>3_mask_1): Ditto.
	(*<shift_insn><mode>3_mask): Ditto.
	(*<shift_insn><mode>3_mask_1): Ditto.
	(*<rotate_insn><mode>3_mask): Ditto.
	(*<rotate_insn><mode>3_mask_1): Ditto.

testsuite/ChangeLog:

	PR target/83467
	* gcc.target/i386/pr83467-1.c: New test.
	* gcc.target/i386/pr83467-2.c: Ditto.

From-SVN: r255949

A number of -fcompare-debug errors on sparc arise as we split a dbr
SEQUENCE back into separate insns to turn the branch into a return.
If we just take the location from the PREV_INSN, it might be a debug
insn without INSN_LOCATION, or an insn with an unrelated location.
But that's silly: each of the SEQUENCEd insns is still an insn with
its own INSN_LOCATION, so use that instead, even though some may have
been adjusted while constructing the SEQUENCE.

for  gcc/ChangeLog

	* reorg.c (make_return_insns): Reemit each insn with its own
	location.

From-SVN: r255948

Statements without side effects, preceded by debug begin stmt markers,
would become a statement list with side effects, although the stmt on
its own would be extracted from the list and remain not having side
effects.  This causes debug info and possibly codegen differences.
This patch fixes it, identifying the situation in which the stmt would
have been extracted from the stmt list, and propagating the side
effects flag from the stmt to the list.

for  gcc/ChangeLog

	PR debug/83419
	* c-family/c-semantics.c (pop_stmt_list): Propagate side
	effects from single nondebug stmt to container list.

for  gcc/testsuite/ChangeLog

	PR debug/83419
	* gcc.dg/pr83419.c: New.

From-SVN: r255947

Our current vector initialisation code will first duplicate
the first element to both lanes, then overwrite the top lane with a new
value.

This duplication can be clunky and wasteful.

Better would be to simply use the fact that we will always be overwriting
the remaining bits, and simply move the first element to the corrcet place
(implicitly zeroing all other bits).

We also need a new pattern in simplify-rtx.c:simplify_ternary_operation ,
to ensure we can still simplify:

  (vec_merge:OUTER
     (vec_duplicate:OUTER x:INNER)
     (subreg:OUTER y:INNER 0)
     (const_int N))

To:

  (vec_concat:OUTER x:INNER y:INNER) or (vec_concat y x)


---
gcc/

	* config/aarch64/aarch64.c (aarch64_expand_vector_init): Modify code
	generation for cases where splatting a value is not useful.
	* simplify-rtx.c (simplify_ternary_operation): Simplify vec_merge
	across a vec_duplicate and a paradoxical subreg forming a vector
	mode to a vec_concat.

gcc/testsuite/

	* gcc.target/aarch64/vect-slp-dup.c: New.

From-SVN: r255946

gcc/

	* combine.c (simplify_set): Do not transform subregs to zero_extends
	if the destination is not a scalar int mode.

From-SVN: r255945

	PR c++/82872
	* convert.c (convert_to_integer_1) <POINTER_TYPE>: Do not return the
	shared zero if the input has overflowed.

From-SVN: r255944

Since support for -mcpu=cortex-a55 and -mcpu=cortex-a75
was added we added support for the +dotprod extension
which these CPUs support.

We already specify as such in the arm-cpus.in entries for
these processors. However the table in driver-arm.c was
not adding +dotproct to the -march string that it generates.

This patch fixes that oversight.
In the future I'd like to get the arm_cpu_table in driver-arm.c
be auto-generated somehow from the arm-cpus.in data so
that we don't have to keep track of discrepancies explicitly...

Bootstrapped and tested on arm-none-linux-gnueabihf.

	* config/arm/driver-arm.c (arm_cpu_table): Specify dotprod
	support for Cortex-A55 and Cortex-A75.

From-SVN: r255943

	* common/config/arm/arm-common.c (compare_opt_names): Add function
	comment.  Use strcmp instead of manual loop.

From-SVN: r255942

2017-12-21  Martin Liska  <mliska@suse.cz>

	PR gcov-profile/83509
	* gcov-dump.c (dump_gcov_file): Do not read info about
	support_unexecuted_blocks for gcda files.

From-SVN: r255941

	PR rtl-optimization/82973
	* emit-rtl.h (valid_for_const_vec_duplicate_p): Rename to ...
	(valid_for_const_vector_p): ... this.
	* emit-rtl.c (valid_for_const_vec_duplicate_p): Rename to ...
	(valid_for_const_vector_p): ... this.  Adjust function comment.
	(gen_vec_duplicate): Adjust caller.
	* optabs.c (expand_vector_broadcast): Likewise.
	* simplify-rtx.c (simplify_const_unary_operation): Don't optimize into
	CONST_VECTOR if some element isn't simplified valid_for_const_vector_p
	constant.
	(simplify_const_binary_operation): Likewise.  Use CONST_FIXED_P macro
	instead of GET_CODE == CONST_FIXED.
	(simplify_subreg): Use CONST_FIXED_P macro instead of
	GET_CODE == CONST_FIXED.

	* gfortran.dg/pr82973.f90: New test.

From-SVN: r255939

	PR rtl-optimization/82973
	* emit-rtl.h (valid_for_const_vec_duplicate_p): Rename to ...
	(valid_for_const_vector_p): ... this.
	* emit-rtl.c (valid_for_const_vec_duplicate_p): Rename to ...
	(valid_for_const_vector_p): ... this.  Adjust function comment.
	(gen_vec_duplicate): Adjust caller.
	* optabs.c (expand_vector_broadcast): Likewise.
	* simplify-rtx.c (simplify_const_unary_operation): Don't optimize into
	CONST_VECTOR if some element isn't simplified valid_for_const_vector_p
	constant.
	(simplify_const_binary_operation): Likewise.  Use CONST_FIXED_P macro
	instead of GET_CODE == CONST_FIXED.
	(simplify_subreg): Use CONST_FIXED_P macro instead of
	GET_CODE == CONST_FIXED.

	* gfortran.dg/pr82973.f90: New test.

From-SVN: r255938

	PR target/83488
	* config/i386/i386.c (ix86_target_string): Move -mavx512vbmi2 and
	-mshstk entries from isa_opts2 to isa_opts and -mhle, -mmovbe,
	-mclzero and -mmwaitx entries from isa_opts to isa_opts2.
	(ix86_option_override_internal): Adjust for
	OPTION_MASK_ISA_{HLE,MOVBE,CLZERO,MWAITX} moving to ix86_isa_flags2
	and OPTION_MASK_ISA_SHSTK moving to ix86_isa_flags.
	(BDESC_VERIFYS): Remove SPECIAL_ARGS2 related checks.
	(ix86_init_mmx_sse_builtins): Remove bdesc_special_args2 handling.
	Use def_builtin2 instead of def_builtin for OPTION_MASK_ISA_MWAITX
	and OPTION_MASK_ISA_CLZERO builtins.  Use def_builtin instead of
	def_builtin2 for CET builtins.
	(ix86_expand_builtin): Remove bdesc_special_args2 handling.  Fix
	up formatting in IX86_BUILTIN_RDPID code.
	* config/i386/i386-builtin.def: Move VBMI2 builtins from SPECIAL_ARGS2
	section to SPECIAL_ARGS and from ARGS2 section to ARGS.
	* config/i386/i386.opt (mavx512vbmi2, mshstk): Move from
	ix86_isa_flags2 to ix86_isa_flags.
	(mhle, mmovbe, mclzero, mmwaitx): Move from ix86_isa_flags to
	ix86_isa_flags2.
	* config/i386/i386-c.c (ix86_target_macros_internal): Check for
	OPTION_MASK_ISA_{CLZERO,MWAITX} in isa_flag2 instead of isa_flag.
	Check for OPTION_MASK_ISA_{SHSTK,AVX512VBMI2} in isa_flag instead
	of isa_flag2.
	* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET):
	Or in OPTION_MASK_ISA_AVX512F_SET.
	(OPTION_MASK_ISA_AVX512F_UNSET): Or in
	OPTION_MASK_ISA_AVX512VBMI2_UNSET.
	(ix86_handle_option): Adjust for
	OPTION_MASK_ISA_{SHSTK,AVX512VBMI2}_*SET being in ix86_isa_flags
	and OPTION_MASK_ISA_{MOVBE,MWAITX,CLZERO}_*SET in ix86_isa_flags2.

	* gcc.target/i386/pr83488.c: New test.

From-SVN: r255937

This patch makes prune_runtime_alias_test_list take the iteration
factor as a poly_int and tracks polynomial offsets internally
as well.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree-data-ref.h (prune_runtime_alias_test_list): Take the
	factor as a poly_uint64 rather than an unsigned HOST_WIDE_INT.
	* tree-data-ref.c (prune_runtime_alias_test_list): Likewise.
	Track polynomial offsets.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255936

This patch makes vect_compute_data_ref_alignment treat DR_INIT as a
poly_int and handles cases in which the calculated misalignment might
not be constant.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree-vect-data-refs.c (vect_compute_data_ref_alignment):
	Treat drb->init as a poly_int.  Fail if its misalignment wrt
	vector_alignment isn't known.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255935

This patch splits the loop versioning threshold out from the
cost model threshold so that the former can become a poly_uint64.
We still use a single test to enforce both limits where possible.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree-vectorizer.h (_loop_vec_info): Add a versioning_threshold
	field.
	(LOOP_VINFO_VERSIONING_THRESHOLD): New macro
	(vect_loop_versioning): Take the loop versioning threshold as a
	separate parameter.
	* tree-vect-loop-manip.c (vect_loop_versioning): Likewise.
	* tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Initialize
	versioning_threshold.
	(vect_analyze_loop_2): Compute the loop versioning threshold
	whenever loop versioning is needed, and store it in the new
	field rather than combining it with the cost model threshold.
	(vect_transform_loop): Update call to vect_loop_versioning.
	Try to combine the loop versioning and cost thresholds here.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255934

This patch makes ivopts handle polynomial address offsets
when recording potential IV uses.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree-ssa-loop-ivopts.h (strip_offset): Return the offset as
	poly_uint64_pod rather than an unsigned HOST_WIDE_INT.
	* tree-loop-distribution.c (classify_builtin_st): Update accordingly.
	* tree-ssa-loop-ivopts.c (iv_use::addr_offset): Change from
	an unsigned HOST_WIDE_INT to a poly_uint64_pod.
	(group_compare_offset): Update accordingly.
	(split_small_address_groups_p): Likewise.
	(record_use): Take addr_offset as a poly_uint64 rather than
	an unsigned HOST_WIDE_INT.
	(strip_offset): Return the offset as a poly_uint64 rather than
	an unsigned HOST_WIDE_INT.
	(record_group_use, split_address_groups): Track polynomial offsets.
	(add_iv_candidate_for_use): Likewise.
	(addr_offset_valid_p): Take the offset as a poly_int64 rather
	than a HOST_WIDE_INT.
	(strip_offset_1): Return the offset as a poly_int64 rather than
	a HOST_WIDE_INT.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255933

This patch changes the offset parameter to get_binfo_at_offset
from HOST_WIDE_INT to poly_int64.  This function probably doesn't
need to handle polynomial offsets in practice, but it's easy
to do and avoids forcing the caller to check first.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree.h (get_binfo_at_offset): Take the offset as a poly_int64
	rather than a HOST_WIDE_INT.
	* tree.c (get_binfo_at_offset): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255932

This patch changes the offset parameter to build_ref_for_offset
from HOST_WIDE_INT to poly_int64.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* ipa-prop.h (build_ref_for_offset): Take the offset as a poly_int64
	rather than a HOST_WIDE_INT.
	* tree-sra.c (build_ref_for_offset): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255931

This patch allows MEM_REF offsets to be polynomial, with mem_ref_offset
now returning a poly_offset_int instead of an offset_int.  The
non-mechanical changes to callers of mem_ref_offset were handled by
previous patches.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* fold-const.h (mem_ref_offset): Return a poly_offset_int rather
	than an offset_int.
	* tree.c (mem_ref_offset): Likewise.
	(build_simple_mem_ref_loc): Treat MEM_REF offsets as poly_ints.
	* builtins.c (get_object_alignment_2): Likewise.
	* expr.c (get_inner_reference, expand_expr_real_1): Likewise.
	* gimple-fold.c (get_base_constructor): Likewise.
	* gimple-ssa-strength-reduction.c (restructure_reference): Likewise.
	* gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref):
	Likewise.
	* ipa-polymorphic-call.c
	(ipa_polymorphic_call_context::ipa_polymorphic_call_context): Likewise.
	* ipa-prop.c (compute_complex_assign_jump_func): Likewise.
	(get_ancestor_addr_info): Likewise.
	* ipa-param-manipulation.c (ipa_get_adjustment_candidate): Likewise.
	* match.pd: Likewise.
	* tree-data-ref.c (dr_analyze_innermost): Likewise.
	* tree-dfa.c (get_addr_base_and_unit_offset_1): Likewise.
	* tree-eh.c (tree_could_trap_p): Likewise.
	* tree-object-size.c (addr_object_size): Likewise.
	* tree-ssa-address.c (copy_ref_info): Likewise.
	* tree-ssa-alias.c (indirect_ref_may_alias_decl_p): Likewise.
	(indirect_refs_may_alias_p): Likewise.
	* tree-ssa-sccvn.c (copy_reference_ops_from_ref): Likewise.
	* tree-ssa.c (maybe_rewrite_mem_ref_base): Likewise.
	(non_rewritable_mem_ref_base): Likewise.
	* tree-vect-data-refs.c (vect_check_gather_scatter): Likewise.
	* tree-vrp.c (vrp_prop::check_array_ref): Likewise.
	* varasm.c (decode_addr_const): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255930

This patch handles polynomial offsets in find_bswap_or_nop_load,
which could be useful for constant-sized data at a variable offset.
It is needed for a later patch to compile.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* gimple-ssa-stor-merging.c (find_bswap_or_nop_load): Track polynomial
	offsets for MEM_REFs.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255929

This patch makes adjust_ptr_info_misalignment take the adjustment
as a poly_uint64 rather than an unsigned int.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree-ssanames.h (adjust_ptr_info_misalignment): Take the increment
	as a poly_uint64 rather than an unsigned int.
	* tree-ssanames.c (adjust_ptr_info_misalignment): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255928

This patch makes the varasm-local addr_const track polynomial offsets.
I'm not sure how useful this is, but it was easier to convert than not.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* varasm.c (addr_const::offset): Change from HOST_WIDE_INT
	to poly_int64.
	(decode_addr_const): Update accordingly.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255927

verify_expr ensured that the size and offset in gimple BIT_FIELD_REFs
satisfied tree_fits_uhwi_p.  This patch extends that so that they can
be poly_uint64s, and adds helper routines for accessing them when the
verify_expr requirements apply.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* tree.h (bit_field_size, bit_field_offset): New functions.
	* hsa-gen.c (gen_hsa_addr): Use them.
	* tree-ssa-forwprop.c (simplify_bitfield_ref): Likewise.
	(simplify_vector_constructor): Likewise.
	* tree-ssa-sccvn.c (copy_reference_ops_from_ref): Likewise.
	* tree-cfg.c (verify_expr): Require the sizes and offsets of a
	BIT_FIELD_REF to be poly_uint64s rather than uhwis.
	* fold-const.c (fold_ternary_loc): Protect tree_to_uhwi with
	tree_fits_uhwi_p.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255926

This patch changes the sizes passed to emit_group_load and
emit_group_store from int to poly_int64.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* expr.h (emit_group_load, emit_group_load_into_temps)
	(emit_group_store): Take the size as a poly_int64 rather than an int.
	* expr.c (emit_group_load_1, emit_group_load): Likewise.
	(emit_group_load_into_temp, emit_group_store): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255925

This patch uses poly_int64 for:

- ira_reuse_stack_slot
- ira_mark_new_stack_slot
- ira_spilled_reg_stack_slot::width

all of which are part of the IRA/reload interface.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* ira-int.h (ira_spilled_reg_stack_slot::width): Change from
	an unsigned int to a poly_uint64.
	* ira.h (ira_reuse_stack_slot, ira_mark_new_stack_slot): Take the
	sizes as poly_uint64s rather than unsigned ints.
	* ira-color.c (ira_reuse_stack_slot, ira_mark_new_stack_slot):
	Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255924

This patch changes the LRA emit_inc routine so that it takes
a poly_int64 rather than an int.

2017-12-21  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* lra-constraints.c (emit_inc): Change inc_amount from an int
	to a poly_int64.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r255923