1. 05 Feb, 2016 19 commits
  2. 04 Feb, 2016 21 commits
    • Test for C99 stdlib.h functions with -std=c++98 · 3555173f
      	PR libstdc++/69626
      	* acinclude.m4 (GLIBCXX_ENABLE_C99): Check C99 stdlib.h functions
      	with -std=c++98 and define _GLIBCXX98_USE_C99_STDLIB.
      	* config.h.in: Regenerate.
      	* configure: Regenerate.
      	* testsuite/21_strings/c_strings/char/69626.cc: New.
      
      From-SVN: r233161
      Jonathan Wakely committed
    • combine: distribute_notes again (PR69567, PR64682) · 171dc40e
      As it happens the patch I did over a year ago for PR64682 isn't quite
      correct.  This is PR69567.  This fixes it.
      
      
      	PR rtl-optimization/64682
      	PR rtl-optimization/69567
      	* combine.c (distribute_notes) <REG_DEAD>: Place the death note
      	before I2 only if the register is both used and set in I2.
      
      From-SVN: r233159
      Segher Boessenkool committed
    • Fix constexpr evaluation of comparisons involving pointer-to-members · 618d6c1c
      gcc/cp/ChangeLog:
      
      	* constexpr.c (cxx_eval_binary_expression): Fold equality
      	comparisons involving PTRMEM_CSTs.
      
      gcc/testsuite/ChangeLog:
      
      	* g++.dg/cpp0x/constexpr-ptrmem5.C: New test.
      
      From-SVN: r233158
      Patrick Palka committed
    • re PR c/69669 (ICE with enum __attribute__((mode(QI)))) · 1066e9b5
      	PR c/69669
      	* c-decl.c (finish_enum): When honoring mode attribute,
      	make sure to use proper TYPE_MIN_VALUE and TYPE_MAX_VALUE.
      
      	* c-c++-common/pr69669.c: New test.
      
      From-SVN: r233154
      Jakub Jelinek committed
    • re PR fortran/69368 (spec2006 test case 416.gamess fails with the g++ 6.0… · 25f738f2
      re PR fortran/69368 (spec2006 test case 416.gamess fails with the g++ 6.0 compiler starting with r232508)
      
      	PR fortran/69368
      	* tree-dfa.c (get_ref_base_and_extent): Remove unreachable code.
      
      From-SVN: r233153
      Jakub Jelinek committed
    • re PR target/69577 (wrong code with -fno-forward-propagate -mavx and 128bit… · cfca2d6d
      re PR target/69577 (wrong code with -fno-forward-propagate -mavx and 128bit arithmetics since r215450)
      
      	PR rtl-optimization/69577
      	Revert:
      	2015-10-29  Richard Henderson  <rth@redhat.com>
      
      	PR target/68124
      	PR rtl-opt/67609
      	* config/i386/i386.c (ix86_cannot_change_mode_class): Tighten
      	sse check to the exact conditions of PR 67609.
      
      From-SVN: r233152
      Uros Bizjak committed
    • Regenerate front page of libstdc++ HTML docs · 15ebf379
      	* doc/html/index.html: Regenerate.
      
      From-SVN: r233151
      Jonathan Wakely committed
    • Update copyright years in libstdc++ manual and add link · dbcda3ee
      	* doc/xml/manual/containers.xml: Add cross-reference to Dual ABI.
      	* doc/xml/manual/spine.xml: Update copyright years and author blurb.
      	* doc/html/*: Regenerate.
      
      From-SVN: r233150
      Jonathan Wakely committed
    • re PR target/69667 (ppc64le -mlra: ICE: Max. number of generated reload insns… · 76255d0d
      re PR target/69667 (ppc64le -mlra: ICE: Max. number of generated reload insns per insn is achieved (90))
      
      [gcc]
      2016-02-04  Michael Meissner  <meissner@linux.vnet.ibm.com>
      
      	PR target/69667
      	* config/rs6000/rs6000.md (mov<mode>_64bit_dm): Use 'd' constraint
      	instead of 'ws', and 'wh' instead of 'wm' since TFmode/IFmode are
      	not allowed into the traditional Altivec registers.
      	(movtd_64bit_nodm): Likewise.
      	(mov<mode>_32bit, FMOVE128_FPR iterator): Likewise.
      
      [gcc/testsuite]
      2016-02-04  Michael Meissner  <meissner@linux.vnet.ibm.com>
      
      	PR target/69667
      	* g++.dg/pr69667.C: New file.
      
      From-SVN: r233147
      Michael Meissner committed
    • Fix jit crash on aarch64 · 0168b518
      gcc/ChangeLog:
      	* config/aarch64/cortex-a57-fma-steering.c
      	(aarch64_register_fma_steering): Remove "static" from arguments
      	to register_pass.
      
      From-SVN: r233146
      David Malcolm committed
    • This patch fixes an exponential issue in ccmp.c. · e0b059b1
      This patch fixes an exponential issue in ccmp.c.  When deciding which ccmp
      expansion to use, the tree nodes gs0 and gs1 are fully expanded twice.  If
      they contain more CCMP opportunities, their subtrees are also expanded twice.
      When the trees are complex the expansion takes exponential time and memory.
      As a workaround in GCC6 compute the cost of the first expansion early, and
      only try the alternative expansion if the cost is low enough.  This rarely
      affects real code, eg. SPECINT2006 has identical codesize.
      
      2016-02-04  Wilco Dijkstra  <wdijkstr@arm.com>
      
          gcc/
      	PR target/69619
      	* ccmp.c (expand_ccmp_expr_1): Avoid evaluating gs0/gs1
      	twice when complex.
      
          gcc/testsuite/
      	PR target/69619
      	* gcc.dg/pr69619.c: Add new test.
      
      From-SVN: r233145
      Wilco Dijkstra committed
    • gcc: invoke: delete -mno-fma4 docs · 56f3bb38
      We don't document the -mno-xxx variants for other flags here, and the
      paragraph here specifically says "Each has a corresponding -mno- option
      to disable use of these instructions".  Drop the -mno-fma4 line.
      
      From-SVN: r233144
      Mike Frysinger committed
    • PR 69577: Invalid RA of destination subregs · 2692b5c8
      In PR 69577 we have:
      
            A: (set (reg:V2TI X) ...)
            B: (set (subreg:TI (reg:V2TI X) 0) ...)
      
      X gets allocated to an AVX register, as usual for V2TI.  The problem is
      that the movti for B doesn't then preserve the other half of X, even
      though the subreg semantics are supposed to guarantee that.
      
      If instead the same value had been set by:
      
            A': (set (subreg:TI (reg:V2TI X) 16) ...)
            B: (set (subreg:TI (reg:V2TI X) 0) ...)
      
      the subreg in A' would have prevented the use of AVX registers for X,
      since you can't directly access the high part.
      
      IMO these are really the same thing.  An alternative way to view it
      is that the original sequence is equivalent to:
      
            A: (set (reg:V2TI X) ...)
            B1: (set (subreg:TI (reg:V2TI X) 0) ...)
            B2: (set (subreg:TI (reg:V2TI X) 16) (subreg:TI (reg:V2TI X) 16))
      
      in which B2 is a no-op and therefore implicit.  The handling ought
      to be the same regardless of whether there is an rtl insn that
      explicitly assigns to (subreg:TI (reg:V2TI X) 16).
      
      This patch implements that idea.  Hopefully the comments explain
      what's going on.
      
      Tested on x86_64-linux-gnu, aarch64-linux-gnu and arm-linux-gnueabihf.
      
      gcc/
      	PR rtl-optimization/69577
      	* reginfo.c (record_subregs_of_mode): Add a partial_def parameter.
      	(find_subregs_of_mode): Update accordingly.  Iterate over partial
      	definitions.
      
      gcc/testsuite/
      	PR rtl-optimization/69577
      	* gcc.target/i386/pr69577.c: New test.
      
      From-SVN: r233143
      Richard Sandiford committed
    • [ARM] Remove neon_reinterpret, use casts · 1d108634
      	* config/arm/arm-protos.h (neon_reinterpret): Remove.
      	* config/arm/arm.c (neon_reinterpret): Remove.
      	* config/arm/arm_neon_builtins.def (vreinterpretv8qi, vreinterpretv4hi,
      	vreinterpretv2si, vreinterpretv2sf, vreinterpretdi, vreinterpretv16qi,
      	vreinterpretv8hi, vreinterpretv4si, vreinterpretv4sf, vreinterpretv2di,
      	vreinterpretti): Remove.
      	* config/arm/neon.md (neon_vreinterpretv8qi<mode>,
      	neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
      	neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>,
      	neon_vreinterpretti<mode>, neon_vreinterpretv16qi<mode>,
      	neon_vreinterpretv8hi<mode>, neon_vreinterpretv4si<mode>,
      	neon_vreinterpretv4sf<mode>, neon_vreinterpretv2di<mode>): Remove.
      	* config/arm/arm_neon.h (vreinterpret_p8_p16, vreinterpret_p8_f32,
      	vreinterpret_p8_p64, vreinterpret_p8_s64, vreinterpret_p8_u64,
      	vreinterpret_p8_s8, vreinterpret_p8_s16, vreinterpret_p8_s32,
      	vreinterpret_p8_u8, vreinterpret_p8_u16, vreinterpret_p8_u32,
      	vreinterpret_p16_p8, vreinterpret_p16_f32, vreinterpret_p16_p64,
      	vreinterpret_p16_s64, vreinterpret_p16_u64, vreinterpret_p16_s8,
      	vreinterpret_p16_s16, vreinterpret_p16_s32, vreinterpret_p16_u8,
      	vreinterpret_p16_u16, vreinterpret_p16_u32, vreinterpret_f32_p8,
      	vreinterpret_f32_p16, vreinterpret_f32_p64, vreinterpret_f32_s64,
      	vreinterpret_f32_u64, vreinterpret_f32_s8, vreinterpret_f32_s16,
      	vreinterpret_f32_s32, vreinterpret_f32_u8, vreinterpret_f32_u16,
      	vreinterpret_f32_u32, vreinterpret_p64_p8, vreinterpret_p64_p16,
      	vreinterpret_p64_f32, vreinterpret_p64_s64, vreinterpret_p64_u64,
      	vreinterpret_p64_s8, vreinterpret_p64_s16, vreinterpret_p64_s32,
      	vreinterpret_p64_u8, vreinterpret_p64_u16, vreinterpret_p64_u32,
      	vreinterpret_s64_p8, vreinterpret_s64_p16, vreinterpret_s64_f32,
      	vreinterpret_s64_p64, vreinterpret_s64_u64, vreinterpret_s64_s8,
      	vreinterpret_s64_s16, vreinterpret_s64_s32, vreinterpret_s64_u8,
      	vreinterpret_s64_u16, vreinterpret_s64_u32, vreinterpret_u64_p8,
      	vreinterpret_u64_p16, vreinterpret_u64_f32, vreinterpret_u64_p64,
      	vreinterpret_u64_s64, vreinterpret_u64_s8, vreinterpret_u64_s16,
      	vreinterpret_u64_s32, vreinterpret_u64_u8, vreinterpret_u64_u16,
      	vreinterpret_u64_u32, vreinterpret_s8_p8, vreinterpret_s8_p16,
      	vreinterpret_s8_f32, vreinterpret_s8_p64, vreinterpret_s8_s64,
      	vreinterpret_s8_u64, vreinterpret_s8_s16, vreinterpret_s8_s32,
      	vreinterpret_s8_u8, vreinterpret_s8_u16, vreinterpret_s8_u32,
      	vreinterpret_s16_p8, vreinterpret_s16_p16, vreinterpret_s16_f32,
      	vreinterpret_s16_p64, vreinterpret_s16_s64, vreinterpret_s16_u64,
      	vreinterpret_s16_s8, vreinterpret_s16_s32, vreinterpret_s16_u8,
      	vreinterpret_s16_u16, vreinterpret_s16_u32, vreinterpret_s32_p8,
      	vreinterpret_s32_p16, vreinterpret_s32_f32, vreinterpret_s32_p64,
      	vreinterpret_s32_s64, vreinterpret_s32_u64, vreinterpret_s32_s8,
      	vreinterpret_s32_s16, vreinterpret_s32_u8, vreinterpret_s32_u16,
      	vreinterpret_s32_u32, vreinterpret_u8_p8, vreinterpret_u8_p16,
      	vreinterpret_u8_f32, vreinterpret_u8_p64, vreinterpret_u8_s64,
      	vreinterpret_u8_u64, vreinterpret_u8_s8, vreinterpret_u8_s16,
      	vreinterpret_u8_s32, vreinterpret_u8_u16, vreinterpret_u8_u32,
      	vreinterpret_u16_p8, vreinterpret_u16_p16, vreinterpret_u16_f32,
      	vreinterpret_u16_p64, vreinterpret_u16_s64, vreinterpret_u16_u64,
      	vreinterpret_u16_s8, vreinterpret_u16_s16, vreinterpret_u16_s32,
      	vreinterpret_u16_u8, vreinterpret_u16_u32, vreinterpret_u32_p8,
      	vreinterpret_u32_p16, vreinterpret_u32_f32, vreinterpret_u32_p64,
      	vreinterpret_u32_s64, vreinterpret_u32_u64, vreinterpret_u32_s8,
      	vreinterpret_u32_s16, vreinterpret_u32_s32, vreinterpret_u32_u8,
      	vreinterpret_u32_u16, vreinterpretq_p8_p16, vreinterpretq_p8_f32,
      	vreinterpretq_p8_p64, vreinterpretq_p8_p128, vreinterpretq_p8_s64,
      	vreinterpretq_p8_u64, vreinterpretq_p8_s8, vreinterpretq_p8_s16,
      	vreinterpretq_p8_s32, vreinterpretq_p8_u8, vreinterpretq_p8_u16,
      	vreinterpretq_p8_u32, vreinterpretq_p16_p8, vreinterpretq_p16_f32,
      	vreinterpretq_p16_p64, vreinterpretq_p16_p128, vreinterpretq_p16_s64,
      	vreinterpretq_p16_u64, vreinterpretq_p16_s8, vreinterpretq_p16_s16,
      	vreinterpretq_p16_s32, vreinterpretq_p16_u8, vreinterpretq_p16_u16,
      	vreinterpretq_p16_u32, vreinterpretq_f32_p8, vreinterpretq_f32_p16,
      	vreinterpretq_f32_p64, vreinterpretq_f32_p128, vreinterpretq_f32_s64,
      	vreinterpretq_f32_u64, vreinterpretq_f32_s8, vreinterpretq_f32_s16,
      	vreinterpretq_f32_s32, vreinterpretq_f32_u8, vreinterpretq_f32_u16,
      	vreinterpretq_f32_u32, vreinterpretq_p64_p8, vreinterpretq_p64_p16,
      	vreinterpretq_p64_f32, vreinterpretq_p64_p128, vreinterpretq_p64_s64,
      	vreinterpretq_p64_u64, vreinterpretq_p64_s8, vreinterpretq_p64_s16,
      	vreinterpretq_p64_s32, vreinterpretq_p64_u8, vreinterpretq_p64_u16,
      	vreinterpretq_p64_u32, vreinterpretq_p128_p8, vreinterpretq_p128_p16,
      	vreinterpretq_p128_f32, vreinterpretq_p128_p64, vreinterpretq_p128_s64,
      	vreinterpretq_p128_u64, vreinterpretq_p128_s8, vreinterpretq_p128_s16,
      	vreinterpretq_p128_s32, vreinterpretq_p128_u8, vreinterpretq_p128_u16,
      	vreinterpretq_p128_u32, vreinterpretq_s64_p8, vreinterpretq_s64_p16,
      	vreinterpretq_s64_f32, vreinterpretq_s64_p64, vreinterpretq_s64_p128,
      	vreinterpretq_s64_u64, vreinterpretq_s64_s8, vreinterpretq_s64_s16,
      	vreinterpretq_s64_s32, vreinterpretq_s64_u8, vreinterpretq_s64_u16,
      	vreinterpretq_s64_u32, vreinterpretq_u64_p8, vreinterpretq_u64_p16,
      	vreinterpretq_u64_f32, vreinterpretq_u64_p64, vreinterpretq_u64_p128,
      	vreinterpretq_u64_s64, vreinterpretq_u64_s8, vreinterpretq_u64_s16,
      	vreinterpretq_u64_s32, vreinterpretq_u64_u8, vreinterpretq_u64_u16,
      	vreinterpretq_u64_u32, vreinterpretq_s8_p8, vreinterpretq_s8_p16,
      	vreinterpretq_s8_f32, vreinterpretq_s8_p64, vreinterpretq_s8_p128,
      	vreinterpretq_s8_s64, vreinterpretq_s8_u64, vreinterpretq_s8_s16,
      	vreinterpretq_s8_s32, vreinterpretq_s8_u8, vreinterpretq_s8_u16,
      	vreinterpretq_s8_u32, vreinterpretq_s16_p8, vreinterpretq_s16_p16,
      	vreinterpretq_s16_f32, vreinterpretq_s16_p64, vreinterpretq_s16_p128,
      	vreinterpretq_s16_s64, vreinterpretq_s16_u64, vreinterpretq_s16_s8,
      	vreinterpretq_s16_s32, vreinterpretq_s16_u8, vreinterpretq_s16_u16,
      	vreinterpretq_s16_u32, vreinterpretq_s32_p8, vreinterpretq_s32_p16,
      	vreinterpretq_s32_f16, vreinterpretq_s32_f32, vreinterpretq_s32_p64,
      	vreinterpretq_s32_p128, vreinterpretq_s32_s64, vreinterpretq_s32_u64,
      	vreinterpretq_s32_s8, vreinterpretq_s32_s16, vreinterpretq_s32_u8,
      	vreinterpretq_s32_u16, vreinterpretq_s32_u32, vreinterpretq_u8_p8,
      	vreinterpretq_u8_p16, vreinterpretq_u8_f32, vreinterpretq_u8_p64,
      	vreinterpretq_u8_p128, vreinterpretq_u8_s64, vreinterpretq_u8_u64,
      	vreinterpretq_u8_s8, vreinterpretq_u8_s16, vreinterpretq_u8_s32,
      	vreinterpretq_u8_u16, vreinterpretq_u8_u32, vreinterpretq_u16_p8,
      	vreinterpretq_u16_p16, vreinterpretq_u16_f32, vreinterpretq_u16_p64,
      	vreinterpretq_u16_p128, vreinterpretq_u16_s64, vreinterpretq_u16_u64,
      	vreinterpretq_u16_s8, vreinterpretq_u16_s16, vreinterpretq_u16_s32,
      	vreinterpretq_u16_u8, vreinterpretq_u16_u32, vreinterpretq_u32_p8,
      	vreinterpretq_u32_p16, vreinterpretq_u32_f32, vreinterpretq_u32_p64,
      	vreinterpretq_u32_p128, vreinterpretq_u32_s64, vreinterpretq_u32_u64,
      	vreinterpretq_u32_s8, vreinterpretq_u32_s16, vreinterpretq_u32_s32,
      	vreinterpretq_u32_u8, vreinterpretq_u32_u16): Rewrite using casts.
      
      From-SVN: r233142
      Alan Lawrence committed
    • Update gcc .po files. · d44cb386
      	* be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
      	ja.po, nl.po, ru.po, sr.po, sv.po, tr.po, uk.po, vi.po, zh_CN.po,
      	zh_TW.po: Update.
      
      From-SVN: r233141
      Joseph Myers committed
    • Update cpplib .po files. · ed84c4aa
      	* be.po, ca.po, da.po, de.po, el.po, eo.po, es.po, fi.po, fr.po,
      	id.po, ja.po, nl.po, pr_BR.po, ru.po, sr.po, sv.po, tr.po, uk.po,
      	vi.po, zh_CN.po, zh_TW.po: Update.
      
      From-SVN: r233140
      Joseph Myers committed
    • re PR sanitizer/69276 (Address sanitizer does not handle heap overflow) · 7db337c2
      Fix PR sanitizer/69276
      
      	* g++.dg/asan/pr69276.C: New test.
      	PR sanitizer/PR69276
      	* asan.c (has_stmt_been_instrumented_p): Instrument gimple calls
      	that are gimple_store_p.
      	(maybe_instrument_call): Likewise.
      
      From-SVN: r233137
      Martin Liska committed
    • aarch64.c (aarch64_legitimize_address): Force register scaling out of memory… · 60d27907
      aarch64.c (aarch64_legitimize_address): Force register scaling out of memory reference and comment why.
      
      
      	* config/aarch64/aarch64.c (aarch64_legitimize_address): Force
      	register scaling out of memory reference and comment why.
      
      From-SVN: r233136
      Bin Cheng committed
    • class.c (find_flexarrays): Don't declare dom variable. · d1243d27
      	* class.c (find_flexarrays): Don't declare dom variable.
      	(diagnose_flexarray): Likewise.
      
      From-SVN: r233135
      Jakub Jelinek committed