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riscv-gcc-1
Commit ffa22984 by David Edelsohn Committed by David Edelsohn
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rs6000.h (MASK_MFCRF): New. 

        * config/rs6000/rs6000.h (MASK_MFCRF): New.
        (TARGET_MFCRF): Test target_flags, not processor type.
        (TARGET_SWITCHES): Add mfcrf and no-mfcrf.
        Change Don't to Do not.
        * config/rs6000/rs6000.c (processors_target_table): Add MASK_MFCRF
        to power4, 970, G5.

From-SVN: r74012
parent e427e694
Showing with 45 additions and 28 deletions
gcc/ChangeLog
2003-11-28 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.h (MASK_MFCRF): New.
(TARGET_MFCRF): Test target_flags, not processor type.
(TARGET_SWITCHES): Add mfcrf and no-mfcrf.
Change Don't to Do not.
* config/rs6000/rs6000.c (processors_target_table): Add MASK_MFCRF
to power4, 970, G5.
2003-11-27 J"orn Rennecke <joern.rennecke@superh.com> 2003-11-27 J"orn Rennecke <joern.rennecke@superh.com>
* cse.c (cse_set_around_loop): When changing a constant load * cse.c (cse_set_around_loop): When changing a constant load
...@@ -3598,7 +3607,7 @@ ...@@ -3598,7 +3607,7 @@
* config/i386/i386.c (x86_this_parameter): Fix typo. * config/i386/i386.c (x86_this_parameter): Fix typo.
203-10-11 Jan Hubicka <jh@suse.cz> 203-10-11 Jan Hubicka <jh@suse.cz>
* Makefile.in (web.o): New. * Makefile.in (web.o): New.
* web.c: New file. * web.c: New file.
......
gcc/config/rs6000/rs6000.c
...@@ -645,7 +645,7 @@ rs6000_override_options (const char *default_cpu) ...@@ -645,7 +645,7 @@ rs6000_override_options (const char *default_cpu)
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
POWER_MASKS}, POWER_MASKS},
{"power4", PROCESSOR_POWER4, {"power4", PROCESSOR_POWER4,
MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS | MASK_MFCRF,
POWER_MASKS}, POWER_MASKS},
{"powerpc", PROCESSOR_POWERPC, {"powerpc", PROCESSOR_POWERPC,
MASK_POWERPC | MASK_NEW_MNEMONICS, MASK_POWERPC | MASK_NEW_MNEMONICS,
...@@ -753,10 +753,10 @@ rs6000_override_options (const char *default_cpu) ...@@ -753,10 +753,10 @@ rs6000_override_options (const char *default_cpu)
MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
{"970", PROCESSOR_POWER4, {"970", PROCESSOR_POWER4,
MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS, MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS | MASK_MFCRF,
POWER_MASKS}, POWER_MASKS},
{"G5", PROCESSOR_POWER4, {"G5", PROCESSOR_POWER4,
MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS, MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS | MASK_MFCRF,
POWER_MASKS}}; POWER_MASKS}};
const size_t ptt_size = ARRAY_SIZE (processor_target_table); const size_t ptt_size = ARRAY_SIZE (processor_target_table);
......
gcc/config/rs6000/rs6000.h
...@@ -187,7 +187,10 @@ extern int target_flags; ...@@ -187,7 +187,10 @@ extern int target_flags;
/* Return small structures in memory (as the AIX ABI requires). */ /* Return small structures in memory (as the AIX ABI requires). */
#define MASK_AIX_STRUCT_RET 0x00040000 #define MASK_AIX_STRUCT_RET 0x00040000
/* The only remaining free bits are 0x00780000. sysv4.h uses /* Use single field mfcr instruction. */
#define MASK_MFCRF 0x00080000
/* The only remaining free bits are 0x00700000. sysv4.h uses
0x00800000 -> 0x40000000, and 0x80000000 is not available 0x00800000 -> 0x40000000, and 0x80000000 is not available
because target_flags is signed. */ because target_flags is signed. */
...@@ -210,6 +213,17 @@ extern int target_flags; ...@@ -210,6 +213,17 @@ extern int target_flags;
#define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC) #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
#define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET) #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
/* Define TARGET_MFCRF if the target assembler supports the optional
field operand for mfcr and the target processor supports the
instruction. */
#ifdef HAVE_AS_MFCRF
#define TARGET_MFCRF (target_flags & MASK_MFCRF)
#else
#define TARGET_MFCRF 0
#endif
#define TARGET_32BIT (! TARGET_64BIT) #define TARGET_32BIT (! TARGET_64BIT)
#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
#define TARGET_UPDATE (! TARGET_NO_UPDATE) #define TARGET_UPDATE (! TARGET_NO_UPDATE)
...@@ -259,19 +273,19 @@ extern int target_flags; ...@@ -259,19 +273,19 @@ extern int target_flags;
{"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \ {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
N_("Use PowerPC General Purpose group optional instructions")},\ N_("Use PowerPC General Purpose group optional instructions")},\
{"no-powerpc-gpopt", - MASK_PPC_GPOPT, \ {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
N_("Don't use PowerPC General Purpose group optional instructions")},\ N_("Do not use PowerPC General Purpose group optional instructions")},\
{"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \ {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
N_("Use PowerPC Graphics group optional instructions")},\ N_("Use PowerPC Graphics group optional instructions")},\
{"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \ {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
N_("Don't use PowerPC Graphics group optional instructions")},\ N_("Do not use PowerPC Graphics group optional instructions")},\
{"powerpc64", MASK_POWERPC64, \ {"powerpc64", MASK_POWERPC64, \
N_("Use PowerPC-64 instruction set")}, \ N_("Use PowerPC-64 instruction set")}, \
{"no-powerpc64", - MASK_POWERPC64, \ {"no-powerpc64", - MASK_POWERPC64, \
N_("Don't use PowerPC-64 instruction set")}, \ N_("Do not use PowerPC-64 instruction set")}, \
{"altivec", MASK_ALTIVEC , \ {"altivec", MASK_ALTIVEC , \
N_("Use AltiVec instructions")}, \ N_("Use AltiVec instructions")}, \
{"no-altivec", - MASK_ALTIVEC , \ {"no-altivec", - MASK_ALTIVEC , \
N_("Don't use AltiVec instructions")}, \ N_("Do not use AltiVec instructions")}, \
{"new-mnemonics", MASK_NEW_MNEMONICS, \ {"new-mnemonics", MASK_NEW_MNEMONICS, \
N_("Use new mnemonics for PowerPC architecture")},\ N_("Use new mnemonics for PowerPC architecture")},\
{"old-mnemonics", -MASK_NEW_MNEMONICS, \ {"old-mnemonics", -MASK_NEW_MNEMONICS, \
...@@ -282,11 +296,11 @@ extern int target_flags; ...@@ -282,11 +296,11 @@ extern int target_flags;
{"fp-in-toc", - MASK_NO_FP_IN_TOC, \ {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
N_("Place floating point constants in TOC")}, \ N_("Place floating point constants in TOC")}, \
{"no-fp-in-toc", MASK_NO_FP_IN_TOC, \ {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
N_("Don't place floating point constants in TOC")},\ N_("Do not place floating point constants in TOC")},\
{"sum-in-toc", - MASK_NO_SUM_IN_TOC, \ {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
N_("Place symbol+offset constants in TOC")}, \ N_("Place symbol+offset constants in TOC")}, \
{"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \ {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
N_("Don't place symbol+offset constants in TOC")},\ N_("Do not place symbol+offset constants in TOC")},\
{"minimal-toc", MASK_MINIMAL_TOC, \ {"minimal-toc", MASK_MINIMAL_TOC, \
"Use only one TOC entry per procedure"}, \ "Use only one TOC entry per procedure"}, \
{"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \ {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
...@@ -294,9 +308,9 @@ extern int target_flags; ...@@ -294,9 +308,9 @@ extern int target_flags;
{"no-minimal-toc", - MASK_MINIMAL_TOC, \ {"no-minimal-toc", - MASK_MINIMAL_TOC, \
N_("Place variable addresses in the regular TOC")},\ N_("Place variable addresses in the regular TOC")},\
{"hard-float", - MASK_SOFT_FLOAT, \ {"hard-float", - MASK_SOFT_FLOAT, \
N_("Use hardware fp")}, \ N_("Use hardware floating point")}, \
{"soft-float", MASK_SOFT_FLOAT, \ {"soft-float", MASK_SOFT_FLOAT, \
N_("Do not use hardware fp")}, \ N_("Do not use hardware floating point")}, \
{"multiple", MASK_MULTIPLE, \ {"multiple", MASK_MULTIPLE, \
N_("Generate load/store multiple instructions")}, \ N_("Generate load/store multiple instructions")}, \
{"no-multiple", - MASK_MULTIPLE, \ {"no-multiple", - MASK_MULTIPLE, \
...@@ -312,11 +326,11 @@ extern int target_flags; ...@@ -312,11 +326,11 @@ extern int target_flags;
{"fused-madd", - MASK_NO_FUSED_MADD, \ {"fused-madd", - MASK_NO_FUSED_MADD, \
N_("Generate fused multiply/add instructions")},\ N_("Generate fused multiply/add instructions")},\
{"no-fused-madd", MASK_NO_FUSED_MADD, \ {"no-fused-madd", MASK_NO_FUSED_MADD, \
N_("Don't generate fused multiply/add instructions")},\ N_("Do not generate fused multiply/add instructions")},\
{"sched-prolog", MASK_SCHED_PROLOG, \ {"sched-prolog", MASK_SCHED_PROLOG, \
""}, \ ""}, \
{"no-sched-prolog", -MASK_SCHED_PROLOG, \ {"no-sched-prolog", -MASK_SCHED_PROLOG, \
N_("Don't schedule the start and end of the procedure")},\ N_("Do not schedule the start and end of the procedure")},\
{"sched-epilog", MASK_SCHED_PROLOG, \ {"sched-epilog", MASK_SCHED_PROLOG, \
""}, \ ""}, \
{"no-sched-epilog", -MASK_SCHED_PROLOG, \ {"no-sched-epilog", -MASK_SCHED_PROLOG, \
...@@ -326,9 +340,13 @@ extern int target_flags; ...@@ -326,9 +340,13 @@ extern int target_flags;
{"svr4-struct-return", - MASK_AIX_STRUCT_RET, \ {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
N_("Return small structures in registers (SVR4 default)")},\ N_("Return small structures in registers (SVR4 default)")},\
{"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \ {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
""},\ ""}, \
{"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \ {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
""},\ ""}, \
{"mfcrf", MASK_MFCRF, \
N_("Generate single field mfcr instruction")}, \
{"no-mfcrf", - MASK_MFCRF, \
N_("Do not generate single field mfcr instruction")},\
SUBTARGET_SWITCHES \ SUBTARGET_SWITCHES \
{"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \ {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
""}} ""}}
...@@ -529,16 +547,6 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops; ...@@ -529,16 +547,6 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
#define DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME \ #define DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME \
(rs6000_cpu == PROCESSOR_POWER4 ? sched_finish_regroup_exact : sched_finish_none) (rs6000_cpu == PROCESSOR_POWER4 ? sched_finish_regroup_exact : sched_finish_none)
/* Define TARGET_MFCRF if the target assembler supports the optional
field operand for mfcr and the target processor supports the
instruction. */
#ifdef HAVE_AS_MFCRF
#define TARGET_MFCRF (rs6000_cpu == PROCESSOR_POWER4)
#else
#define TARGET_MFCRF 0
#endif
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
#define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
...@@ -555,7 +563,7 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops; ...@@ -555,7 +563,7 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
defined, is executed once just after all the command options have defined, is executed once just after all the command options have
been parsed. been parsed.
Don't use this macro to turn on various extra optimizations for Do not use this macro to turn on various extra optimizations for
`-O'. That is what `OPTIMIZATION_OPTIONS' is for. `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
On the RS/6000 this is used to define the target cpu type. */ On the RS/6000 this is used to define the target cpu type. */
......
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