Commit ff881d52 by J"orn Rennecke Committed by Joern Rennecke

sh.h (binary_logical_operator): Declare.

	* sh.h (binary_logical_operator): Declare.
	* sh.c (binary_logical_operator): New function.
	* sh.md (xordi3+1): New combiner splitter pattern.

From-SVN: r58675
parent e8e4c876
Thu Oct 31 12:45:55 2002 J"orn Rennecke <joern.rennecke@superh.com>
* sh.h (binary_logical_operator): Declare.
* sh.c (binary_logical_operator): New function.
* sh.md (xordi3+1): New combiner splitter pattern.
2002-10-31 David O'Brien <obrien@FreeBSD.org> 2002-10-31 David O'Brien <obrien@FreeBSD.org>
* config/sparc/freebsd.h (TRANSFER_FROM_TRAMPOLINE): Define * config/sparc/freebsd.h (TRANSFER_FROM_TRAMPOLINE): Define
......
...@@ -6177,6 +6177,25 @@ binary_float_operator (op, mode) ...@@ -6177,6 +6177,25 @@ binary_float_operator (op, mode)
} }
int int
binary_logical_operator (op, mode)
rtx op;
enum machine_mode mode;
{
if (GET_MODE (op) != mode)
return 0;
switch (GET_CODE (op))
{
case IOR:
case AND:
case XOR:
return 1;
default:
break;
}
return 0;
}
int
equality_comparison_operator (op, mode) equality_comparison_operator (op, mode)
rtx op; rtx op;
enum machine_mode mode; enum machine_mode mode;
......
...@@ -3225,6 +3225,7 @@ extern int rtx_equal_function_value_matters; ...@@ -3225,6 +3225,7 @@ extern int rtx_equal_function_value_matters;
{"arith_reg_operand", {SUBREG, REG}}, \ {"arith_reg_operand", {SUBREG, REG}}, \
{"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \ {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
{"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \ {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
{"binary_logical_operator", {AND, IOR, XOR}}, \
{"commutative_float_operator", {PLUS, MULT}}, \ {"commutative_float_operator", {PLUS, MULT}}, \
{"equality_comparison_operator", {EQ,NE}}, \ {"equality_comparison_operator", {EQ,NE}}, \
{"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \ {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
......
...@@ -2038,6 +2038,33 @@ ...@@ -2038,6 +2038,33 @@
xor %1, %2, %0 xor %1, %2, %0
xori %1, %2, %0" xori %1, %2, %0"
[(set_attr "type" "arith_media")]) [(set_attr "type" "arith_media")])
;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
;; converts 2 * sign extend -> logical op into logical op -> sign extend
(define_split
[(set (match_operand:DI 0 "arith_reg_operand" "")
(sign_extend:DI (match_operator 4 "binary_logical_operator"
[(match_operand 1 "any_register_operand" "")
(match_operand 2 "any_register_operand" "")])))]
"TARGET_SHMEDIA"
[(set (match_dup 5) (match_dup 4))
(set (match_dup 0) (sign_extend:DI (match_dup 5)))]
"
{
enum machine_mode inmode = GET_MODE (operands[1]);
int regno, offset = 0;
if (GET_CODE (operands[0]) == SUBREG)
{
offset = SUBREG_BYTE (operands[0]);
operands[0] = SUBREG_REG (operands[0]);
}
if (GET_CODE (operands[0]) != REG)
abort ();
if (! TARGET_LITTLE_ENDIAN)
offset += 8 - GET_MODE_SIZE (inmode);
operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
}")
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
;; Shifts and rotates ;; Shifts and rotates
......
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