Skip to content

R
riscv-gcc-1
Commit feca59ff by Wilco Dijkstra Committed by Jiong Wang
Options

[AArch64][4/5] Remove redundant code 

2015-09-20  Wilco Dijkstra  <wdijkstr@arm.com>

	* config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Remove
	redundant immediate generation code.

From-SVN: r227949
parent 8fcbb4e3
Showing with 5 additions and 60 deletions
gcc/ChangeLog
2015-09-20 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Remove
redundant immediate generation code.
2015-09-20 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.c (aarch64_bitmasks): Remove.
(AARCH64_NUM_BITMASKS): Remove.
(aarch64_bitmasks_cmp): Remove.
gcc/config/aarch64/aarch64.c
......@@ -1437,8 +1437,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
int i;
bool first;
unsigned HOST_WIDE_INT val, val2;
bool subtargets;
rtx subtarget;
int one_match, zero_match, first_not_ffff_match;
int num_insns = 0;
......@@ -1468,7 +1466,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
/* Remaining cases are all for DImode. */
val = INTVAL (imm);
subtargets = optimize && can_create_pseudo_p ();
one_match = 0;
zero_match = 0;
......@@ -1506,63 +1503,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
if (zero_match == 2)
goto simple_sequence;
mask = 0x0ffff0000UL;
for (i = 16; i < 64; i += 16, mask <<= 16)
{
HOST_WIDE_INT comp = mask & ~(mask - 1);
if (aarch64_uimm12_shift (val - (val & mask)))
{
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
emit_insn (gen_rtx_SET (subtarget, GEN_INT (val & mask)));
emit_insn (gen_adddi3 (dest, subtarget,
GEN_INT (val - (val & mask))));
}
num_insns += 2;
return num_insns;
}
else if (aarch64_uimm12_shift (-(val - ((val + comp) & mask))))
{
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
emit_insn (gen_rtx_SET (subtarget,
GEN_INT ((val + comp) & mask)));
emit_insn (gen_adddi3 (dest, subtarget,
GEN_INT (val - ((val + comp) & mask))));
}
num_insns += 2;
return num_insns;
}
else if (aarch64_uimm12_shift (val - ((val - comp) | ~mask)))
{
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
emit_insn (gen_rtx_SET (subtarget,
GEN_INT ((val - comp) | ~mask)));
emit_insn (gen_adddi3 (dest, subtarget,
GEN_INT (val - ((val - comp) | ~mask))));
}
num_insns += 2;
return num_insns;
}
else if (aarch64_uimm12_shift (-(val - (val | ~mask))))
{
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
emit_insn (gen_rtx_SET (subtarget, GEN_INT (val | ~mask)));
emit_insn (gen_adddi3 (dest, subtarget,
GEN_INT (val - (val | ~mask))));
}
num_insns += 2;
return num_insns;
}
}
if (zero_match != 2 && one_match != 2)
{
/* Try emitting a bitmask immediate with a movk replacing 16 bits.
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment