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riscv-gcc-1
Commit fe2d45c7 by Fariborz Jahanian Committed by Fariborz Jahanian
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Fix vec_merge patterns for Altivec ppc. 

OKed by Geoff Keating.

From-SVN: r99779
parent 7b8a92e1
Showing with 96 additions and 33 deletions
gcc/ChangeLog
2005-05-16 Fariborz Jahanian <fjahanian@apple.com>
* config/rs6000/altivec.md (altivec_vmrghb, altivec_vmrghh,
altivec_vmrghw, altivec_vmrglb, altivec_vmrglh, altivec_vmrglw):
New values for vec_select definitions and bitmask for element
selection.
2005-05-16 Kazu Hirata <kazu@cs.umass.edu>
* dwarf2out.c (used_rtx_varray): Rename to used_rtx_array.
......
gcc/config/rs6000/altivec.md
......@@ -673,24 +673,40 @@
(define_insn "altivec_vmrghb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
(parallel [(const_int 8)
(parallel [(const_int 0)
(const_int 8)
(const_int 1)
(const_int 9)
(const_int 2)
(const_int 10)
(const_int 11)
(const_int 3)
(const_int 11)
(const_int 4)
(const_int 12)
(const_int 5)
(const_int 13)
(const_int 14)
(const_int 15)
(const_int 6)
(const_int 14)
(const_int 7)
(const_int 15)]))
(vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
(parallel [(const_int 8)
(const_int 0)
(const_int 9)
(const_int 1)
(const_int 10)
(const_int 2)
(const_int 3)
(const_int 11)
(const_int 3)
(const_int 12)
(const_int 4)
(const_int 13)
(const_int 5)
(const_int 14)
(const_int 6)
(const_int 15)
(const_int 7)]))
(match_operand:V16QI 2 "register_operand" "v")
(const_int 255)))]
(const_int 21845)))]
"TARGET_ALTIVEC"
"vmrghb %0,%1,%2"
[(set_attr "type" "vecperm")])
......@@ -698,16 +714,24 @@
(define_insn "altivec_vmrghh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
(parallel [(const_int 4)
(parallel [(const_int 0)
(const_int 4)
(const_int 1)
(const_int 5)
(const_int 2)
(const_int 6)
(const_int 7)
(const_int 3)
(const_int 7)]))
(vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
(parallel [(const_int 4)
(const_int 0)
(const_int 5)
(const_int 1)
(const_int 6)
(const_int 2)
(const_int 7)
(const_int 3)]))
(match_operand:V8HI 2 "register_operand" "v")
(const_int 15)))]
(const_int 85)))]
"TARGET_ALTIVEC"
"vmrghh %0,%1,%2"
[(set_attr "type" "vecperm")])
......@@ -715,67 +739,99 @@
(define_insn "altivec_vmrghw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
(parallel [(const_int 0)
(const_int 2)
(const_int 1)
(const_int 3)]))
(vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
(parallel [(const_int 2)
(const_int 3)
(const_int 0)
(const_int 0)
(const_int 3)
(const_int 1)]))
(match_operand:V4SI 2 "register_operand" "v")
(const_int 12)))]
(const_int 5)))]
"TARGET_ALTIVEC"
"vmrghw %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vmrglb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
(parallel [(const_int 0)
(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
(parallel [(const_int 8)
(const_int 0)
(const_int 9)
(const_int 1)
(const_int 10)
(const_int 2)
(const_int 3)
(const_int 11)
(const_int 3)
(const_int 12)
(const_int 4)
(const_int 13)
(const_int 5)
(const_int 6)
(const_int 7)
(const_int 14)
(const_int 6)
(const_int 15)
(const_int 7)]))
(vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
(parallel [(const_int 0)
(const_int 8)
(const_int 1)
(const_int 9)
(const_int 2)
(const_int 10)
(const_int 11)
(const_int 3)
(const_int 11)
(const_int 4)
(const_int 12)
(const_int 5)
(const_int 13)
(const_int 6)
(const_int 14)
(const_int 7)
(const_int 15)]))
(match_operand:V16QI 1 "register_operand" "v")
(const_int 255)))]
(const_int 21845)))]
"TARGET_ALTIVEC"
"vmrglb %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vmrglh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
(parallel [(const_int 0)
(vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
(parallel [(const_int 4)
(const_int 0)
(const_int 5)
(const_int 1)
(const_int 6)
(const_int 2)
(const_int 3)
(const_int 7)
(const_int 3)]))
(vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
(parallel [(const_int 0)
(const_int 4)
(const_int 1)
(const_int 5)
(const_int 2)
(const_int 6)
(const_int 3)
(const_int 7)]))
(match_operand:V8HI 1 "register_operand" "v")
(const_int 15)))]
(const_int 85)))]
"TARGET_ALTIVEC"
"vmrglh %0,%1,%2"
[(set_attr "type" "vecperm")])
(define_insn "altivec_vmrglw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
(vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
(parallel [(const_int 2)
(const_int 0)
(const_int 3)
(const_int 1)]))
(vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
(parallel [(const_int 0)
(const_int 1)
(const_int 2)
(const_int 2)
(const_int 1)
(const_int 3)]))
(match_operand:V4SI 1 "register_operand" "v")
(const_int 12)))]
(const_int 5)))]
"TARGET_ALTIVEC"
"vmrglw %0,%1,%2"
[(set_attr "type" "vecperm")])
......
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