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Commit fe19a83d by Kazu Hirata Committed by Kazu Hirata
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milli64.S: Fix comment formatting. 

	* config/pa/milli64.S: Fix comment formatting.
	* config/pa/pa-64.h: Likewise.
	* config/pa/pa-linux.h: Likewise.
	* config/pa/pa-protos.h: Likewise.
	* config/pa/pa.c: Likewise.
	* config/pa/pa.h: Likewise.
	* config/pa/pa32-linux.h: Likewise.
	* config/pa/pa32-regs.h: Likewise.
	* config/pa/pa64-hpux.h: Likewise.
	* config/pa/pa64-regs.h: Likewise.
	* config/pa/som.h: Likewise.

From-SVN: r46930
parent b64a6a11
Showing with 68 additions and 54 deletions
gcc/ChangeLog
2001-11-11 Kazu Hirata <kazu@hxi.com>
* config/pa/milli64.S: Fix comment formatting.
* config/pa/pa-64.h: Likewise.
* config/pa/pa-linux.h: Likewise.
* config/pa/pa-protos.h: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/pa.h: Likewise.
* config/pa/pa32-linux.h: Likewise.
* config/pa/pa32-regs.h: Likewise.
* config/pa/pa64-hpux.h: Likewise.
* config/pa/pa64-regs.h: Likewise.
* config/pa/som.h: Likewise.
2001-11-11 Joseph S. Myers <jsm28@cam.ac.uk>
* doc/gcc.texi: Move several chapters out to ...
......
gcc/config/pa/milli64.S
......@@ -388,7 +388,7 @@ LSYM(small_divisor)
#if defined(pa64)
/* Clear the upper 32 bits of the arg1 register. We are working with */
/* small divisors (and 32 bit integers) We must not be mislead */
/* by "1" bits left in the upper 32 bits. */
/* by "1" bits left in the upper 32 bits. */
depd %r0,31,32,%r25
#endif
blr,n arg1,r0
......@@ -1765,7 +1765,7 @@ LSYM(l4)
sub,> 0,a1,t0 /* otherwise negate both and */
combt,<=,n a0,t0,LREF(l2) /* swap back if |a0|<|a1| */
sub 0,a0,a1
movb,tr,n t0,a0,LREF(l2) /* 10th inst. */
movb,tr,n t0,a0,LREF(l2) /* 10th inst. */
LSYM(l0) r__r_t0 /* add in this partial product */
LSYM(l1) a0__256a0 /* a0 <<= 8 ****************** */
......@@ -1773,7 +1773,7 @@ LSYM(l2) zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
LSYM(l3) blr t0,0 /* case on these 8 bits ****** */
extru a1,23,24,a1 /* a1 >>= 8 ****************** */
/*16 insts before this. */
/*16 insts before this. */
/* a0 <<= 8 ************************** */
LSYM(x0) a1_ne_0_b_l2 ! a0__256a0 ! MILLIRETN ! nop
LSYM(x1) a1_ne_0_b_l1 ! r__r_a0 ! MILLIRETN ! nop
......@@ -2031,7 +2031,7 @@ LSYM(x252) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
LSYM(x253) t0__64a0 ! t0__t0ma0 ! b_e_t0 ! t0__4t0_a0
LSYM(x254) t0__128a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
LSYM(x255) t0__256a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
/*1040 insts before this. */
/*1040 insts before this. */
LSYM(ret_t0) MILLIRET
LSYM(e_t0) r__r_t0
LSYM(e_shift) a1_ne_0_b_l2
......
gcc/config/pa/pa-64.h
......@@ -105,7 +105,7 @@ Boston, MA 02111-1307, USA. */
} \
while (0)
/* Nonzero if we do not know how to pass TYPE solely in registers. */
/* Nonzero if we do not know how to pass TYPE solely in registers. */
#define MUST_PASS_IN_STACK(MODE,TYPE) \
((TYPE) != 0 \
&& (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
......
gcc/config/pa/pa-linux.h
......@@ -81,7 +81,7 @@ Boston, MA 02111-1307, USA. */
#define BSS_SECTION_ASM_OP "\t.section\t.bss"
/* Output at beginning of assembler file. We override the definition
from <linux.h> so that we can get the proper .LEVEL directive. */
from <linux.h> so that we can get the proper .LEVEL directive. */
#undef ASM_FILE_START
#define ASM_FILE_START(FILE) \
do \
......
gcc/config/pa/pa-protos.h
......@@ -19,13 +19,13 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#ifdef RTX_CODE
/* Prototype function used in MACHINE_DEPENDENT_REORG macro. */
/* Prototype function used in MACHINE_DEPENDENT_REORG macro. */
extern void pa_reorg PARAMS ((rtx));
/* Prototype function used in various macros. */
/* Prototype function used in various macros. */
extern int symbolic_operand PARAMS ((rtx, enum machine_mode));
/* Used in insn-*.c. */
/* Used in insn-*.c. */
extern int following_call PARAMS ((rtx));
extern int function_label_operand PARAMS ((rtx, enum machine_mode));
extern int lhs_lshift_cint_operand PARAMS ((rtx, enum machine_mode));
......@@ -126,7 +126,7 @@ extern int insn_refs_are_delayed PARAMS ((rtx));
/* Prototype function used in macro ASM_OUTPUT_MI_THUNK. */
extern void pa_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
/* Prototype function used in macro CONST_OK_FOR_LETTER_P. */
/* Prototype function used in macro CONST_OK_FOR_LETTER_P. */
extern int zdepi_cint_p PARAMS ((unsigned HOST_WIDE_INT));
extern struct rtx_def *hppa_builtin_saveregs PARAMS ((void));
......
gcc/config/pa/pa.c
......@@ -245,7 +245,7 @@ symbolic_expression_p (x)
register rtx x;
{
/* Strip off any HIGH. */
/* Strip off any HIGH. */
if (GET_CODE (x) == HIGH)
x = XEXP (x, 0);
......@@ -807,7 +807,7 @@ hppa_legitimize_address (x, oldx, mode)
if (flag_pic)
return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
/* Strip off CONST. */
/* Strip off CONST. */
if (GET_CODE (x) == CONST)
x = XEXP (x, 0);
......@@ -3245,7 +3245,7 @@ load_reg (reg, disp, base)
The function epilogue should not depend on the current stack
pointer! It should use the frame pointer only. This is mandatory
because of alloca; we also take advantage of it to omit stack
adjustments before returning. */
adjustments before returning. */
static void
pa_output_function_epilogue (file, size)
......@@ -3292,7 +3292,7 @@ hppa_expand_epilogue ()
/* Try to restore RP early to avoid load/use interlocks when
RP gets used in the return (bv) instruction. This appears to still
be necessary even when we schedule the prologue and epilogue. */
be necessary even when we schedule the prologue and epilogue. */
if (regs_ever_live [2])
{
ret_off = TARGET_64BIT ? -16 : -20;
......@@ -3992,7 +3992,7 @@ pa_adjust_insn_length (insn, length)
return 4;
/* Adjust dbra insn with short backwards conditional branch with
unfilled delay slot -- only for case where counter is in a
general register register. */
general register register. */
else if (GET_CODE (pat) == PARALLEL
&& GET_CODE (XVECEXP (pat, 0, 1)) == SET
&& GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
......@@ -4037,7 +4037,7 @@ print_operand (file, x, code)
fputs (reg_names[REGNO (x) + 1], file);
return;
case 'r':
/* A register or zero. */
/* A register or zero. */
if (x == const0_rtx
|| (x == CONST0_RTX (DFmode))
|| (x == CONST0_RTX (SFmode)))
......@@ -4048,7 +4048,7 @@ print_operand (file, x, code)
else
break;
case 'f':
/* A register or zero (floating point). */
/* A register or zero (floating point). */
if (x == const0_rtx
|| (x == CONST0_RTX (DFmode))
|| (x == CONST0_RTX (SFmode)))
......@@ -4376,7 +4376,7 @@ print_operand (file, x, code)
output_addr_const (file, x);
}
/* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
/* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
void
output_global_address (file, x, round_constant)
......@@ -4505,7 +4505,7 @@ import_milli (code)
}
/* The register constraints have put the operands and return value in
the proper registers. */
the proper registers. */
const char *
output_mul_insn (unsignedp, insn)
......@@ -4516,7 +4516,7 @@ output_mul_insn (unsignedp, insn)
return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
}
/* Emit the rtl for doing a division by a constant. */
/* Emit the rtl for doing a division by a constant. */
/* Do magic division millicodes exist for this value? */
static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
......@@ -4524,7 +4524,7 @@ static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
/* We'll use an array to keep track of the magic millicodes and
whether or not we've used them already. [n][0] is signed, [n][1] is
unsigned. */
unsigned. */
static int div_milli[16][2];
......@@ -4608,7 +4608,7 @@ output_div_insn (operands, unsignedp, insn)
gen_rtx_SYMBOL_REF (SImode, buf));
}
}
/* Divisor isn't a special constant. */
/* Divisor isn't a special constant. */
else
{
if (unsignedp)
......@@ -4626,7 +4626,7 @@ output_div_insn (operands, unsignedp, insn)
}
}
/* Output a $$rem millicode to do mod. */
/* Output a $$rem millicode to do mod. */
const char *
output_mod_insn (unsignedp, insn)
......@@ -4836,7 +4836,7 @@ function_arg_padding (mode, type)
size = int_size_in_bytes (type) * BITS_PER_UNIT;
else
return upward; /* Don't know if this is right, but */
/* same as old definition. */
/* same as old definition. */
}
else
size = GET_MODE_BITSIZE (mode);
......@@ -4898,7 +4898,7 @@ hppa_builtin_saveregs ()
offset, 0, 0, OPTAB_LIB_WIDEN));
}
/* Store general registers on the stack. */
/* Store general registers on the stack. */
dest = gen_rtx_MEM (BLKmode,
plus_constant (current_function_internal_arg_pointer,
-16));
......@@ -4949,7 +4949,7 @@ hppa_va_arg (valist, type)
if (TARGET_64BIT)
{
/* Every argument in PA64 is passed by value (including large structs).
Arguments with size greater than 8 must be aligned 0 MOD 16. */
Arguments with size greater than 8 must be aligned 0 MOD 16. */
size = int_size_in_bytes (type);
if (size > UNITS_PER_WORD)
......@@ -5814,7 +5814,7 @@ output_millicode_call (insn, call_dest)
else if (TARGET_PORTABLE_RUNTIME)
{
xoperands[0] = call_dest;
/* Get the address of our target into %r29. */
/* Get the address of our target into %r29. */
output_asm_insn ("ldil L%%%0,%%r29", xoperands);
output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
......@@ -6384,7 +6384,7 @@ non_hard_reg_operand (op, mode)
}
/* Return 1 if INSN branches forward. Should be using insn_addresses
to avoid walking through all the insns... */
to avoid walking through all the insns... */
static int
forward_branch_p (insn)
rtx insn;
......@@ -7236,7 +7236,7 @@ function_arg (cum, mode, type, named, incoming)
/* If this arg would be passed totally in registers or totally on the stack,
then this routine should return zero. It is currently called only for
the 64-bit target. */
the 64-bit target. */
int
function_arg_partial_nregs (cum, mode, type, named)
CUMULATIVE_ARGS *cum;
......@@ -7251,13 +7251,13 @@ function_arg_partial_nregs (cum, mode, type, named)
offset = 1;
if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
/* Arg fits fully into registers. */
/* Arg fits fully into registers. */
return 0;
else if (cum->words + offset >= max_arg_words)
/* Arg fully on the stack. */
/* Arg fully on the stack. */
return 0;
else
/* Arg is split. */
/* Arg is split. */
return max_arg_words - cum->words - offset;
}
......
gcc/config/pa/pa.h
......@@ -154,7 +154,7 @@ extern int target_flags;
#define TARGET_64BIT 0
#endif
/* Generate code for ELF32 ABI. */
/* Generate code for ELF32 ABI. */
#ifndef TARGET_ELF32
#define TARGET_ELF32 0
#endif
......@@ -340,7 +340,7 @@ extern int target_flags;
The definition is be an initializer for an array of structures. Each
array element has have three elements: the switch name, one of the
enumeration codes ADD or DELETE to indicate whether the string should be
inserted or deleted, and the string to be inserted or deleted. */
inserted or deleted, and the string to be inserted or deleted. */
#define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
/* Make gcc agree with <machine/ansi.h> */
......@@ -438,7 +438,7 @@ extern int target_flags;
/* No data type wants to be aligned rounder than this. */
#define BIGGEST_ALIGNMENT 64
/* Get around hp-ux assembler bug, and make strcpy of constants fast. */
/* Get around hp-ux assembler bug, and make strcpy of constants fast. */
#define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
......@@ -653,7 +653,7 @@ extern struct rtx_def *hppa_pic_save_rtx PARAMS ((void));
/* The weird HPPA calling conventions require a minimum of 48 bytes on
the stack: 16 bytes for register saves, and 32 bytes for magic.
This is the difference between the logical top of stack and the
actual sp. */
actual sp. */
#define STACK_POINTER_OFFSET \
(TARGET_64BIT ? -(current_function_outgoing_args_size + 16): -32)
......@@ -740,7 +740,7 @@ struct hppa_args {int words, nargs_prototype, indirect; };
(CUM).indirect = 0, \
(CUM).nargs_prototype = 1000
/* Figure out the size in words of the function argument. */
/* Figure out the size in words of the function argument. */
#define FUNCTION_ARG_SIZE(MODE, TYPE) \
((((MODE) != BLKmode \
......@@ -820,7 +820,7 @@ struct hppa_args {int words, nargs_prototype, indirect; };
For args passed entirely in registers or entirely in memory, zero. */
/* For PA32 there are never split arguments. PA64, on the other hand, can
pass arguments partially in registers and partially in memory. */
pass arguments partially in registers and partially in memory. */
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
(TARGET_64BIT ? function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) : 0)
......@@ -840,7 +840,7 @@ struct hppa_args {int words, nargs_prototype, indirect; };
/* Arguments larger than eight bytes are passed by invisible reference */
/* PA64 does not pass anything by invisible reference. */
/* PA64 does not pass anything by invisible reference. */
#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
(TARGET_64BIT \
? 0 \
......@@ -849,7 +849,7 @@ struct hppa_args {int words, nargs_prototype, indirect; };
/* PA64 does not pass anything by invisible reference.
This should be undef'ed for 64bit, but we'll see if this works. The
problem is that we can't test TARGET_64BIT from the preprocessor. */
problem is that we can't test TARGET_64BIT from the preprocessor. */
#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
(TARGET_64BIT \
? 0 \
......@@ -1004,7 +1004,7 @@ extern int may_call_alloca;
emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (FNADDR)); \
start_addr = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (CXT)); \
/* Create a fat pointer for the trampoline. */ \
/* Create a fat pointer for the trampoline. */ \
end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
start_addr = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
emit_move_insn (gen_rtx_MEM (Pmode, start_addr), end_addr); \
......@@ -1470,7 +1470,7 @@ do { \
information).
On the HP-PA we use this to indicate if a symbol is in text or
data space. Also, function labels need special treatment. */
data space. Also, function labels need special treatment. */
#define TEXT_SPACE_P(DECL)\
(TREE_CODE (DECL) == FUNCTION_DECL \
......@@ -1569,7 +1569,7 @@ while (0)
/* Add any extra modes needed to represent the condition code.
HPPA floating comparisons produce condition codes. */
HPPA floating comparisons produce condition codes. */
#define EXTRA_CC_MODES CC(CCFPmode, "CCFP")
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
......@@ -1592,7 +1592,7 @@ while (0)
#define NO_FUNCTION_CSE
/* Define this to be nonzero if shift instructions ignore all but the low-order
few bits. */
few bits. */
#define SHIFT_COUNT_TRUNCATED 1
/* Compute the cost of computing a constant rtl expression RTX
......
gcc/config/pa/pa32-linux.h
......@@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* Turn off various SOM crap we don't want. */
/* Turn off various SOM crap we don't want. */
#undef TARGET_ELF32
#define TARGET_ELF32 1
......
gcc/config/pa/pa32-regs.h
......@@ -17,7 +17,7 @@
differently: the left and right halves of registers are addressable
as 32 bit registers. So, we will set things up like the 68k which
has different fp units: define separate register sets for the 1.0
and 1.1 fp units. */
and 1.1 fp units. */
#define FIRST_PSEUDO_REGISTER 89 /* 32 general regs + 56 fp regs +
+ 1 shift reg */
......@@ -168,12 +168,12 @@
force this to be an even register is it cannot hold the full mode. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \
/* On 1.0 machines, don't allow wide non-fp modes in fp regs. */ \
/* On 1.0 machines, don't allow wide non-fp modes in fp regs. */ \
: !TARGET_PA_11 && FP_REGNO_P (REGNO) \
? GET_MODE_SIZE (MODE) <= 4 || GET_MODE_CLASS (MODE) == MODE_FLOAT \
: FP_REGNO_P (REGNO) \
? GET_MODE_SIZE (MODE) <= 4 || ((REGNO) & 1) == 0 \
/* Make wide modes be in aligned registers. */ \
/* Make wide modes be in aligned registers. */ \
: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
|| (GET_MODE_SIZE (MODE) <= 4 * UNITS_PER_WORD && ((REGNO) & 1) == 0)))
......@@ -232,7 +232,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. Register 0, the "condition code" register,
is in no class. */
is in no class. */
#define REG_CLASS_CONTENTS \
{{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \
......
gcc/config/pa/pa64-hpux.h
......@@ -107,7 +107,7 @@ do { \
The definitions say how to change sections to the .init and .fini
sections. This is the same for all known svr4 assemblers. */
/* ??? For the time being, we aren't using init sections. */
/* ??? For the time being, we aren't using init sections. */
#if 0
#define INIT_SECTION_ASM_OP "\t.section\t.init"
#define FINI_SECTION_ASM_OP "\t.section\t.fini"
......
gcc/config/pa/pa64-regs.h
......@@ -161,7 +161,7 @@ Boston, MA 02111-1307, USA. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) == 0 \
? (MODE) == CCmode || (MODE) == CCFPmode \
/* Make wide modes be in aligned registers. */ \
/* Make wide modes be in aligned registers. */ \
: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
|| (GET_MODE_SIZE (MODE) <= 2 * UNITS_PER_WORD && ((REGNO) & 1) == 0)))
......@@ -220,7 +220,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. Register 0, the "condition code" register,
is in no class. */
is in no class. */
#define REG_CLASS_CONTENTS \
{{0x00000000, 0x00000000}, /* NO_REGS */ \
......
gcc/config/pa/som.h
......@@ -42,7 +42,7 @@ Boston, MA 02111-1307, USA. */
last_function_decl = current_function_decl; \
sym_lineno += 1; }
/* gdb needs a null N_SO at the end of each file for scattered loading. */
/* gdb needs a null N_SO at the end of each file for scattered loading. */
#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END
#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME) \
......@@ -267,7 +267,7 @@ do { \
So, we force exception information into the data section. */
#define TARGET_ASM_EXCEPTION_SECTION data_section
/* Define the .bss section for ASM_OUTPUT_LOCAL to use. */
/* Define the .bss section for ASM_OUTPUT_LOCAL to use. */
#define EXTRA_SECTIONS in_readonly_data
......
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