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lvzhengyang
riscv-gcc-1
Commits
fe03d631
Commit
fe03d631
authored
Mar 18, 2003
by
Ulrich Weigand
Committed by
Ulrich Weigand
Mar 18, 2003
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* config/s390/s390.md ("movti", "movhi", "movqi"): Add "type" attribute.
From-SVN: r64542
parent
45183e03
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gcc/ChangeLog
View file @
fe03d631
2003-03-18 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.md ("movti", "movhi", "movqi"): Add "type" attribute.
Tue Mar 18 19:22:57 CET 2003 Jan Hubicka <jh@suse.cz>
Tue Mar 18 19:22:57 CET 2003 Jan Hubicka <jh@suse.cz>
* alias.c (rtx_equal_for_memref_p): Assume that X and Y has been
* alias.c (rtx_equal_for_memref_p): Assume that X and Y has been
...
...
gcc/config/s390/s390.md
View file @
fe03d631
...
@@ -913,7 +913,8 @@
...
@@ -913,7 +913,8 @@
#
#
#
#
mvc
\\
t%O0(16,%R0),%1"
mvc
\\
t%O0(16,%R0),%1"
[
(set_attr "op_type" "RSE,RSE,NN,NN,SS")
]
)
[
(set_attr "op_type" "RSE,RSE,NN,NN,SS")
(set_attr "type" "lm,stm,
*,*
,cs")])
(define_split
(define_split
[
(set (match_operand:TI 0 "nonimmediate_operand" "")
[
(set (match_operand:TI 0 "nonimmediate_operand" "")
...
@@ -1225,7 +1226,8 @@
...
@@ -1225,7 +1226,8 @@
lh
\\
t%0,%1
lh
\\
t%0,%1
sth
\\
t%1,%0
sth
\\
t%1,%0
mvc
\\
t%O0(2,%R0),%1"
mvc
\\
t%O0(2,%R0),%1"
[
(set_attr "op_type" "RR,RI,RX,RX,SS")
]
)
[
(set_attr "op_type" "RR,RI,RX,RX,SS")
(set_attr "type" "lr,
*,*
,store,cs")])
(define_peephole2
(define_peephole2
[
(set (match_operand:HI 0 "register_operand" "")
[
(set (match_operand:HI 0 "register_operand" "")
...
@@ -1266,7 +1268,8 @@
...
@@ -1266,7 +1268,8 @@
stc
\\
t%1,%0
stc
\\
t%1,%0
mvi
\\
t%0,%b1
mvi
\\
t%0,%b1
mvc
\\
t%O0(1,%R0),%1"
mvc
\\
t%O0(1,%R0),%1"
[
(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
]
)
[
(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
(set_attr "type" "lr,
*,*
,store,store,cs")])
(define_peephole2
(define_peephole2
[
(set (match_operand:QI 0 "nonimmediate_operand" "")
[
(set (match_operand:QI 0 "nonimmediate_operand" "")
...
...
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