(logical patterns): Tune to give better code for immediate values.

From-SVN: r7476

gcc/config/a29k/a29k.md

@@ -102,12 +102,13 @@
    andn %0,%1,%C2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "srcb_operand" "rI"))
-		(match_operand:SI 2 "gpc_reg_operand" "r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
+		(match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
   ""
-  "andn %0,%2,%1")
-
+  "@
+   andn %0,%2,%1
+   nor %0,%1,%C2")
 
 ;; CALLI
 ;;
@@ -1196,7 +1197,7 @@
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		(not:SI (match_operand:SI 2 "srcb_operand" "rI"))))]
+		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
   ""
   "nand %0,%1,%2")
 
@@ -1204,24 +1205,18 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		(match_operand:SI 2 "const_int_operand" "K")))]
-  "((unsigned) ~ INTVAL (operands[2])) < 256"
+  ; Match TARGET_29050 in "orn" pattern for slightly better reload.
+  "! TARGET_29050 && ((unsigned) ~ INTVAL (operands[2])) < 256"
   "nand %0,%1,%C2")
 
 ;; NOR
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-		(not:SI (match_operand:SI 2 "srcb_operand" "rI"))))]
+		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
   ""
   "nor %0,%1,%2")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-		(match_operand:SI 2 "const_int_operand" "K")))]
-  "((unsigned) ~ INTVAL (operands[2])) < 256"
-  "nor %0,%1,%C2")
-
 (define_insn "one_cmplsi2"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
@@ -1246,12 +1241,21 @@
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
-		(match_operand:SI 2 "srcb_operand" "rI,K")))]
+		(match_operand:SI 2 "and_operand" "rI,K")))]
   "TARGET_29050"
   "@
    or %0,%1,%2
    orn %0,%1,%C2")
 
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
+		(match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
+  "TARGET_29050"
+  "@
+   orn %0,%2,%1
+   nand %0,%1,%C2")
+
 
 ;; SLL (also used by move insn)
 (define_insn "nop"
@@ -1512,17 +1516,20 @@
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
-			(match_operand:SI 2 "srcb_operand" "rI"))))]
+			(match_operand:SI 2 "gpc_reg_operand" "r"))))]
   ""
   "xnor %0,%1,%2")
 
 ;; XOR
+
 (define_insn "xorsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
-		(match_operand:SI 2 "srcb_operand" "rI")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+		(match_operand:SI 2 "and_operand" "rI,K")))]
   ""
-  "xor %0,%1,%2")
+  "@
+   xor %0,%1,%2
+   xnor %0,%1,%C2")
 
 ;; Can use XOR to negate floating-point values, but we are better off not doing
 ;; it that way on the 29050 so it can combine with the fmac insns.