re PR target/59316 (gcc.dg/atomic/c11-atomic-exec-5.c FAILs on Solaris/SPARC)

	PR target/59316
	* config/sparc/sparc.h (SPARC_LOW_FE_EXCEPT_VALUES): Define.
	* config/sparc/sol2.h (SPARC_LOW_FE_EXCEPT_VALUES): Redefine.
	* config/sparc/sparc.c (TARGET_INIT_BUILTINS): Move around.
	(TARGET_BUILTIN_DECL): Define.
	(TARGET_ATOMIC_ASSIGN_EXPAND_FENV): Likewise.
	(sparc32_initialize_trampoline): Adjust call to gen_flush.
	(enum sparc_builtins): New enumeral type.
	(sparc_builtins): New static array.
	(sparc_builtins_icode): Likewise.
	(def_builtin): Accept a separate icode and save the result.
	(def_builtin_const): Likewise.
	(sparc_fpu_init_builtins): New function.
	(sparc_vis_init_builtins): Pass the builtin code.
	(sparc_init_builtins): Call it if TARGET_FPU.
	(sparc_builtin_decl): New function.
	(sparc_expand_builtin): Deal with SPARC_BUILTIN_{LD,ST}FSR.
	(sparc_handle_vis_mul8x16): Use the builtin code.
	(sparc_fold_builtin): Likewise.  Deal with SPARC_BUILTIN_{LD,ST}FSR
	and SPARC_BUILTIN_PDISTN.
	(compound_expr): New helper function.
	(sparc_atomic_assign_expand_fenv): New function.
	* config/sparc/sparc.md (unspecv): Reorder values, add UNSPECV_LDFSR
	and UNSPECV_STFSR.
	(flush, flushdi): Merge into single pattern.
	(ldfsr): New instruction.
	(stfsr): Likewise.

From-SVN: r205735

gcc/ChangeLog

+2013-12-06  Eric Botcazou  <ebotcazou@adacore.com>
+
+	PR target/59316
+	* config/sparc/sparc.h (SPARC_LOW_FE_EXCEPT_VALUES): Define.
+	* config/sparc/sol2.h (SPARC_LOW_FE_EXCEPT_VALUES): Redefine.
+	* config/sparc/sparc.c (TARGET_INIT_BUILTINS): Move around.
+	(TARGET_BUILTIN_DECL): Define.
+	(TARGET_ATOMIC_ASSIGN_EXPAND_FENV): Likewise.
+	(sparc32_initialize_trampoline): Adjust call to gen_flush.
+	(enum sparc_builtins): New enumeral type.
+	(sparc_builtins): New static array.
+	(sparc_builtins_icode): Likewise.
+	(def_builtin): Accept a separate icode and save the result.
+	(def_builtin_const): Likewise.
+	(sparc_fpu_init_builtins): New function.
+	(sparc_vis_init_builtins): Pass the builtin code.
+	(sparc_init_builtins): Call it if TARGET_FPU.
+	(sparc_builtin_decl): New function.
+	(sparc_expand_builtin): Deal with SPARC_BUILTIN_{LD,ST}FSR.
+	(sparc_handle_vis_mul8x16): Use the builtin code.
+	(sparc_fold_builtin): Likewise.  Deal with SPARC_BUILTIN_{LD,ST}FSR
+	and SPARC_BUILTIN_PDISTN.
+	(compound_expr): New helper function.
+	(sparc_atomic_assign_expand_fenv): New function.
+	* config/sparc/sparc.md (unspecv): Reorder values, add UNSPECV_LDFSR
+	and UNSPECV_STFSR.
+	(flush, flushdi): Merge into single pattern.
+	(ldfsr): New instruction.
+	(stfsr): Likewise.
+
 2013-12-06  Oleg Endo  <olegendo@gcc.gnu.org>
 
 	* asan.c: Remove struct tags when referring to class varpool_node.

gcc/config/sparc/sol2.h

@@ -406,3 +406,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 
 #undef SUN_INTEGER_MULTIPLY_64
 #define SUN_INTEGER_MULTIPLY_64 1
+
+#undef SPARC_LOW_FE_EXCEPT_VALUES
+#define SPARC_LOW_FE_EXCEPT_VALUES 1

gcc/config/sparc/sparc.h

@@ -1777,3 +1777,6 @@ extern int sparc_indent_opcode;
 #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL
 #define SUBTARGET_DEFAULT_MEMORY_MODEL	SMM_DEFAULT
 #endif
+
+/* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1.  */
+#define SPARC_LOW_FE_EXCEPT_VALUES 0

gcc/config/sparc/sparc.md

@@ -96,13 +96,19 @@
 
 (define_c_enum "unspecv" [
   UNSPECV_BLOCKAGE
+  UNSPECV_PROBE_STACK_RANGE
+
   UNSPECV_FLUSHW
-  UNSPECV_FLUSH
   UNSPECV_SAVEW
-  UNSPECV_CAS
-  UNSPECV_SWAP
+
+  UNSPECV_FLUSH
+
   UNSPECV_LDSTUB
-  UNSPECV_PROBE_STACK_RANGE
+  UNSPECV_SWAP
+  UNSPECV_CAS
+
+  UNSPECV_LDFSR
+  UNSPECV_STFSR
 ])
 
 (define_constants
@@ -6783,22 +6789,26 @@
 
 ;; Special pattern for the FLUSH instruction.
 
-; We do SImode and DImode versions of this to quiet down genrecog's complaints
-; of the define_insn otherwise missing a mode.  We make "flush", aka
-; gen_flush, the default one since sparc_initialize_trampoline uses
-; it on SImode mem values.
-
-(define_insn "flush"
-  [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
+(define_insn "flush<P:mode>"
+  [(unspec_volatile [(match_operand:P 0 "memory_operand" "m")] UNSPECV_FLUSH)]
   ""
   { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
   [(set_attr "type" "iflush")])
 
-(define_insn "flushdi"
-  [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
-  ""
-  { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
-  [(set_attr "type" "iflush")])
+;; Special insns to load and store the 32-bit FP Status Register.
+
+(define_insn "ldfsr"
+  [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_LDFSR)]
+  "TARGET_FPU"
+  "ld\t%0, %%fsr"
+  [(set_attr "type" "load")])
+
+(define_insn "stfsr"
+  [(set (match_operand:SI 0 "memory_operand" "=m")
+        (unspec_volatile:SI [(const_int 0)] UNSPECV_STFSR))]
+  "TARGET_FPU"
+  "st\t%%fsr, %0"
+  [(set_attr "type" "store")])
 
 
 ;; Find first set instructions.

gcc/testsuite/ChangeLog

+2013-12-06  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* gcc.target/sparc/pdistn.c: New test.
+	* gcc.target/sparc/pdistn-2.c: Likewise.
+
 2013-12-06  Richard Biener  <rguenther@suse.de>
 
 	PR tree-optimization/59058

gcc/testsuite/gcc.target/sparc/pdistn-2.c

+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis3 -O1 -fdump-tree-optimized" } */
+
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+#define _(A) (unsigned char)A
+
+long foo () {
+  vec8 a = { _(1), _(2), _(3), _(4), _(5), _(6), _(7), _(255) };
+  vec8 b = { _(2), _(4), _(8), _(16), _(32), _(64), _(128), _(8) };
+  return __builtin_vis_pdistn (a, b);
+}
+
+/* { dg-final { scan-assembler-not "pdistn\t%" } } */
+/* { dg-final { scan-tree-dump "return 473" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */

gcc/testsuite/gcc.target/sparc/pdistn.c

+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis3" } */
+
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+long foo (vec8 a, vec8 b) {
+  return __builtin_vis_pdistn (a, b);
+}
+
+/* { dg-final { scan-assembler-times "pdistn\t%" 1 } } */