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riscv-gcc-1
Commit fdd695fd by Paul Brook Committed by Paul Brook
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arm-protots.h (vfp_mem_operand): Rename ... 

	* config/arm/arm-protots.h (vfp_mem_operand): Rename ...
	(arm_coproc_mem_operand): ... To this.
	* config/arm/arm.c (arm_legitimate_address_p): Allow ldrd modes.
	(arm_legitimate_index_p): Ditto.
	(vfp_mem_operand): Rename ...
	(arm_coproc_mem_operand): ... To this.  Handle writeback modes.
	(vfp_secondary_reload_class): Use it.
	(output_move_double): Use doubleword load/store instructions.
	(arm_hard_regno_mode_ok): Only allow even reg pairs for ldrd.
	* config/arm/arm.h (TARGET_LDRD): Define.
	(EXTRA_CONSTRAINT_STR_ARM): Add 'Uy'.
	* config/gcc/arm/arm.md (arm_movdi): Allow all valid memory operands.
	New splitter for invalid doubleword loads.
	* config/arm/iwmmxt.md (iwmmxt_arm_movdi): Use Uy constraint.
	* config/arm/vfp.md (arm_movdi_vfp): Allow all valid memory operands.
	* doc/md.texi: Document Uy constraint.

From-SVN: r81543
parent 74e94435
Showing with 52 additions and 7 deletions
gcc/ChangeLog
2004-05-06 Paul Brook <paul@codesourcery.com>
* config/arm/arm-protots.h (vfp_mem_operand): Rename ...
(arm_coproc_mem_operand): ... To this.
* config/arm/arm.c (arm_legitimate_address_p): Allow ldrd modes.
(arm_legitimate_index_p): Ditto.
(vfp_mem_operand): Rename ...
(arm_coproc_mem_operand): ... To this. Handle writeback modes.
(vfp_secondary_reload_class): Use it.
(output_move_double): Use doubleword load/store instructions.
(arm_hard_regno_mode_ok): Only allow even reg pairs for ldrd.
* config/arm/arm.h (TARGET_LDRD): Define.
(EXTRA_CONSTRAINT_STR_ARM): Add 'Uy'.
* config/gcc/arm/arm.md (arm_movdi): Allow all valid memory operands.
New splitter for invalid doubleword loads.
* config/arm/iwmmxt.md (iwmmxt_arm_movdi): Use Uy constraint.
* config/arm/vfp.md (arm_movdi_vfp): Allow all valid memory operands.
* doc/md.texi: Document Uy constraint.
2004-05-05 Jan Hubicka <jh@suse.cz>
PR opt/14980
......
gcc/config/arm/arm-protos.h
......@@ -100,7 +100,7 @@ extern int cirrus_general_operand (rtx, enum machine_mode);
extern int cirrus_register_operand (rtx, enum machine_mode);
extern int cirrus_shift_const (rtx, enum machine_mode);
extern int cirrus_memory_offset (rtx);
extern int vfp_mem_operand (rtx);
extern int arm_coproc_mem_operand (rtx, bool);
extern int vfp_compare_operand (rtx, enum machine_mode);
extern int arm_float_compare_operand (rtx, enum machine_mode);
extern int arm_no_early_store_addr_dep (rtx, rtx);
......
gcc/config/arm/arm.h
......@@ -306,6 +306,7 @@ extern GTY(()) rtx aof_pic_label;
? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
: (target_flags & THUMB_FLAG_BACKTRACE))
#define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)
#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
/* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */
#ifndef SUBTARGET_SWITCHES
......@@ -1292,6 +1293,7 @@ enum reg_class
accessed without using a load.
'U' Prefixes an extended memory constraint where:
'Uv' is an address valid for VFP load/store insns.
'Uy' is an address valid for iwmmxt load/store insns.
'Uq' is an address valid for ldrsb. */
#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
......@@ -1302,7 +1304,8 @@ enum reg_class
&& CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
((C) == 'T') ? cirrus_memory_offset (OP) : \
((C) == 'U' && (STR)[1] == 'v') ? vfp_mem_operand (OP) : \
((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
((C) == 'U' && (STR)[1] == 'q') \
? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
: 0)
......
gcc/config/arm/arm.md
......@@ -4073,7 +4073,7 @@
)
(define_insn "*arm_movdi"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, o<>")
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r ,m")
(match_operand:DI 1 "di_operand" "rIK,mi,r"))]
"TARGET_ARM
&& !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
......@@ -4087,6 +4087,26 @@
(set_attr "neg_pool_range" "*,1008,*")]
)
;; We can't actually do base+index doubleword loads if the index and
;; destination overlap. Split here so that we at least have chance to
;; schedule.
(define_split
[(set (match_operand:DI 0 "s_register_operand" "")
(mem:DI (plus:SI (match_operand:SI 1 "s_register_operand" "")
(match_operand:SI 2 "s_register_operand" ""))))]
"TARGET_LDRD
&& reg_overlap_mentioned_p (operands[0], operands[1])
&& reg_overlap_mentioned_p (operands[0], operands[2])"
[(set (match_dup 4)
(plus:SI (match_dup 1)
(match_dup 2)))
(set (match_dup 0)
(mem:DI (match_dup 4)))]
"
operands[4] = gen_rtx_REG (SImode, REGNO(operands[0]));
"
)
;;; ??? This should have alternatives for constants.
;;; ??? This was originally identical to the movdf_insn pattern.
;;; ??? The 'i' constraint looks funny, but it should always be replaced by
......
gcc/config/arm/iwmmxt.md
......@@ -64,8 +64,8 @@
[(set_attr "predicable" "yes")])
(define_insn "*iwmmxt_arm_movdi"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, o<>,y,y,yr,y,yrm")
(match_operand:DI 1 "di_operand" "rIK,mi,r ,y,yr,y,yrm,y"))]
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy")
(match_operand:DI 1 "di_operand" "rIK,mi,r,y,yr,y,yrUy,y"))]
"TARGET_REALLY_IWMMXT"
"*
{
......
gcc/config/arm/vfp.md
......@@ -136,8 +136,8 @@
;; DImode moves
(define_insn "*arm_movdi_vfp"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,o<>,w,r,w,w ,Uv")
(match_operand:DI 1 "di_operand" "rIK,mi,r ,r,w,w,Uvi,w"))]
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
(match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
"*
switch (which_alternative)
......
gcc/doc/md.texi
......@@ -1363,6 +1363,9 @@ A symbol in the text segment of the current file
@item Uv
A memory reference suitable for VFP load/store insns (reg+constant offset)
@item Uy
A memory reference suitable for iWMMXt load/store instructions.
@item Uq
A memory reference suitable for for the ARMv4 ldrsb instruction.
......
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