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riscv-gcc-1
Commit fd3b43f2 by Dale Johannesen Committed by Dale Johannesen
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rs6000.h: CPP_CPU_SPEC: add mcpu=7400. 

         * config/rs6000/rs6000.h:  CPP_CPU_SPEC: add mcpu=7400.
         ASM_CPU_SPEC: Ditto.
         RTX_COSTS: Fix timing info for 7450 multiply.
         * config/rs6000/rs6000.md:  Fix timing info for 7450 imul.
         Allow floats to be kept in int regs in movsf_low,
         movsf_low_st (Darwin only)

From-SVN: r48117
parent 9aa86737
Showing with 27 additions and 62 deletions
gcc/ChangeLog
2001-12-17 Dale Johannesen <dalej@apple.com>
* config/rs6000/rs6000.h: CPP_CPU_SPEC: add mcpu=7400.
ASM_CPU_SPEC: Ditto.
RTX_COSTS: Fix timing info for 7450 multiply.
* config/rs6000/rs6000.md: Fix timing info for 7450 imul.
Allow floats to be kept in int regs in movsf_low,
movsf_low_st (Darwin only)
2001-12-17 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.c (vrsave_operation): Recognize SETs in
......
gcc/config/rs6000/rs6000.h
......@@ -76,6 +76,7 @@ Boston, MA 02111-1307, USA. */
%{mcpu=604e: -D_ARCH_PPC} \
%{mcpu=620: -D_ARCH_PPC} \
%{mcpu=740: -D_ARCH_PPC} \
%{mcpu=7400: -D_ARCH_PPC} \
%{mcpu=7450: -D_ARCH_PPC} \
%{mcpu=750: -D_ARCH_PPC} \
%{mcpu=801: -D_ARCH_PPC} \
......@@ -114,6 +115,7 @@ Boston, MA 02111-1307, USA. */
%{mcpu=604e: -mppc} \
%{mcpu=620: -mppc} \
%{mcpu=740: -mppc} \
%{mcpu=7400: -mppc} \
%{mcpu=7450: -mppc} \
%{mcpu=750: -mppc} \
%{mcpu=801: -mppc} \
......@@ -2073,7 +2075,7 @@ do { \
push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
OPNUM, TYPE); \
goto WIN; \
goto WIN; \
} \
if (GET_CODE (X) == PLUS \
&& GET_CODE (XEXP (X, 0)) == REG \
......@@ -2326,12 +2328,15 @@ do { \
return COSTS_N_INSNS (5); \
case PROCESSOR_PPC603: \
case PROCESSOR_PPC7400: \
case PROCESSOR_PPC7450: \
case PROCESSOR_PPC750: \
return (GET_CODE (XEXP (X, 1)) != CONST_INT \
? COSTS_N_INSNS (5) \
: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
case PROCESSOR_PPC7450: \
return (GET_CODE (XEXP (X, 1)) != CONST_INT \
? COSTS_N_INSNS (4) \
: COSTS_N_INSNS (3)); \
case PROCESSOR_PPC403: \
case PROCESSOR_PPC604: \
return COSTS_N_INSNS (4); \
......
gcc/config/rs6000/rs6000.md
......@@ -359,7 +359,7 @@
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc7450"))
4 4)
4 2)
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul2,imul3")
......@@ -7608,20 +7608,24 @@
(set_attr "length" "4")])
(define_insn "movsf_low"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
(mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"lfs %0,lo16(%2)(%1)"
"@
lfs %0,lo16(%2)(%1)
{l|lwz} %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_insn "movsf_low_st"
[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b")
(match_operand 2 "" "")))
(match_operand:SF 0 "gpc_reg_operand" "f"))]
(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"stfs %0,lo16(%2)(%1)"
"@
stfs %0,lo16(%2)(%1)
{st|stw} %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
......@@ -9378,59 +9382,6 @@
&& ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
&& addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
"stfq%U0%X0 %1,%0")
;; APPLE LOCAL peephole2 to eliminate unneeded computation of FP const
;; address in register. If lo part of address is reused (i.e. reg0
;; is not dead), make the change in the fp load anyway (for scheduling)
;; but we switch the instructions in case op0==op1.
;; (define_peephole2
;; [(set (match_operand:SI 0 "gpc_reg_operand" "")
;; (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "")
;; (match_operand:SI 2 "" "")))
;; (set (match_operand:DF 3 "gpc_reg_operand" "")
;; (mem:DF (match_dup 0)))]
;; "TARGET_HARD_FLOAT
;; && peep2_reg_dead_p(2, operands[0])
;; && FP_REGNO_P (REGNO (operands[3]))"
;; [(set (match_dup 3) (mem:DF (lo_sum:SI (match_dup 1) (match_dup 2))))]
;; "")
;; (define_peephole2
;; [(set (match_operand:SI 0 "gpc_reg_operand" "")
;; (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "")
;; (match_operand:SI 2 "" "")))
;; (set (match_operand:DF 3 "gpc_reg_operand" "")
;; (mem:DF (match_dup 0)))]
;; "TARGET_HARD_FLOAT
;; && !peep2_reg_dead_p(2, operands[0])
;; && FP_REGNO_P (REGNO (operands[3]))"
;; [(set (match_dup 3) (mem:DF (lo_sum:SI (match_dup 1) (match_dup 2))))
;; (set (match_dup 0) (lo_sum:SI (match_dup 1) (match_dup 2)))]
;; "")
;; (define_peephole2
;; [(set (match_operand:SI 0 "gpc_reg_operand" "")
;; (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "")
;; (match_operand:SI 2 "" "")))
;; (set (match_operand:SF 3 "gpc_reg_operand" "")
;; (mem:SF (match_dup 0)))]
;; "TARGET_HARD_FLOAT
;; && peep2_reg_dead_p(2, operands[0])
;; && FP_REGNO_P (REGNO (operands[3]))"
;; [(set (match_dup 3) (mem:SF (lo_sum:SI (match_dup 1) (match_dup 2))))]
;; "")
;; (define_peephole2
;; [(set (match_operand:SI 0 "gpc_reg_operand" "")
;; (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "")
;; (match_operand:SI 2 "" "")))
;; (set (match_operand:SF 3 "gpc_reg_operand" "")
;; (mem:SF (match_dup 0)))]
;; "TARGET_HARD_FLOAT
;; && !peep2_reg_dead_p(2, operands[0])
;; && FP_REGNO_P (REGNO (operands[3]))"
;; [(set (match_dup 3) (mem:SF (lo_sum:SI (match_dup 1) (match_dup 2))))
;; (set (match_dup 0) (lo_sum:SI (match_dup 1) (match_dup 2)))]
;; "")
;; Next come insns related to the calling sequence.
;;
......
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