Commit fc4d140a by Jiong Wang Committed by Jiong Wang

[Patch/expand] Cost instruction sequences when doing left wide shift

Patch background details:

    https://gcc.gnu.org/ml/gcc-patches/2015-08/msg01147.html

gcc/
  PR rtl-optimization/67421
  * expr.c (expand_expr_real_2): Cost instrcution sequences when doing left wide
  shift tranformation.

From-SVN: r227629
parent fb155425
2015-09-10 Jiong Wang <jiong.wang@arm.com>
PR rtl-optimization/67421
* expr.c (expand_expr_real_2): Cost instrcution sequences when doing
left wide shift tranformation.
2015-09-10 Claudiu Zissulescu <claziss@synopsys.com> 2015-09-10 Claudiu Zissulescu <claziss@synopsys.com>
* common/config/arc/arc-common.c: Remove references to A5. * common/config/arc/arc-common.c: Remove references to A5.
......
...@@ -8892,7 +8892,6 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode, ...@@ -8892,7 +8892,6 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
&& ! unsignedp && ! unsignedp
&& mode == GET_MODE_WIDER_MODE (word_mode) && mode == GET_MODE_WIDER_MODE (word_mode)
&& GET_MODE_SIZE (mode) == 2 * GET_MODE_SIZE (word_mode) && GET_MODE_SIZE (mode) == 2 * GET_MODE_SIZE (word_mode)
&& ! have_insn_for (ASHIFT, mode)
&& TREE_CONSTANT (treeop1) && TREE_CONSTANT (treeop1)
&& TREE_CODE (treeop0) == SSA_NAME) && TREE_CODE (treeop0) == SSA_NAME)
{ {
...@@ -8908,6 +8907,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode, ...@@ -8908,6 +8907,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
&& ((TREE_INT_CST_LOW (treeop1) + GET_MODE_BITSIZE (rmode)) && ((TREE_INT_CST_LOW (treeop1) + GET_MODE_BITSIZE (rmode))
>= GET_MODE_BITSIZE (word_mode))) >= GET_MODE_BITSIZE (word_mode)))
{ {
rtx_insn *seq, *seq_old;
unsigned int high_off = subreg_highpart_offset (word_mode, unsigned int high_off = subreg_highpart_offset (word_mode,
mode); mode);
rtx low = lowpart_subreg (word_mode, op0, mode); rtx low = lowpart_subreg (word_mode, op0, mode);
...@@ -8918,6 +8918,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode, ...@@ -8918,6 +8918,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
- TREE_INT_CST_LOW (treeop1)); - TREE_INT_CST_LOW (treeop1));
tree rshift = build_int_cst (TREE_TYPE (treeop1), ramount); tree rshift = build_int_cst (TREE_TYPE (treeop1), ramount);
start_sequence ();
/* dest_high = src_low >> (word_size - C). */ /* dest_high = src_low >> (word_size - C). */
temp = expand_variable_shift (RSHIFT_EXPR, word_mode, low, temp = expand_variable_shift (RSHIFT_EXPR, word_mode, low,
rshift, dest_high, unsignedp); rshift, dest_high, unsignedp);
...@@ -8930,7 +8931,28 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode, ...@@ -8930,7 +8931,28 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
if (temp != dest_low) if (temp != dest_low)
emit_move_insn (dest_low, temp); emit_move_insn (dest_low, temp);
seq = get_insns ();
end_sequence ();
temp = target ; temp = target ;
if (have_insn_for (ASHIFT, mode))
{
bool speed_p = optimize_insn_for_speed_p ();
start_sequence ();
rtx ret_old = expand_variable_shift (code, mode, op0,
treeop1, target,
unsignedp);
seq_old = get_insns ();
end_sequence ();
if (seq_cost (seq, speed_p)
>= seq_cost (seq_old, speed_p))
{
seq = seq_old;
temp = ret_old;
}
}
emit_insn (seq);
} }
} }
} }
......
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