Commit fc182093 by Kazu Hirata Committed by Kazu Hirata

h8300.md (*extzv_1_r_h8300): Correct the insn length.

	* config/h8300/h8300.md (*extzv_1_r_h8300): Correct the insn
	length.
	(*extzv_1_r_h8300hs): Likewise.
	(*extzv_1_r_inv_h8300): Likewise.
	(*extzv_1_r_inv_h8300hs): Likewise.

From-SVN: r61115
parent 0f399e5f
2003-01-09 Kazu Hirata <kazu@cs.umass.edu> 2003-01-09 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.md (*extzv_1_r_h8300): Correct the insn
length.
(*extzv_1_r_h8300hs): Likewise.
(*extzv_1_r_inv_h8300): Likewise.
(*extzv_1_r_inv_h8300hs): Likewise.
2003-01-09 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.h (PREDICATE_CODES): New. * config/h8300/h8300.h (PREDICATE_CODES): New.
2003-01-09 Kazu Hirata <kazu@cs.umass.edu> 2003-01-09 Kazu Hirata <kazu@cs.umass.edu>
......
...@@ -2403,7 +2403,7 @@ ...@@ -2403,7 +2403,7 @@
;; Normal loads with a 32bit destination. ;; Normal loads with a 32bit destination.
;; ;;
(define_insn "" (define_insn "*extzv_1_r_h8300"
[(set (match_operand:SI 0 "register_operand" "=&r") [(set (match_operand:SI 0 "register_operand" "=&r")
(zero_extract:SI (match_operand:HI 1 "register_operand" "r") (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
(const_int 1) (const_int 1)
...@@ -2412,9 +2412,9 @@ ...@@ -2412,9 +2412,9 @@
&& INTVAL (operands[2]) < 16" && INTVAL (operands[2]) < 16"
"* return output_simode_bld (0, operands);" "* return output_simode_bld (0, operands);"
[(set_attr "cc" "clobber") [(set_attr "cc" "clobber")
(set_attr "length" "6")]) (set_attr "length" "8")])
(define_insn "" (define_insn "*extzv_1_r_h8300hs"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r") (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1) (const_int 1)
...@@ -2423,13 +2423,13 @@ ...@@ -2423,13 +2423,13 @@
&& INTVAL (operands[2]) < 16" && INTVAL (operands[2]) < 16"
"* return output_simode_bld (0, operands);" "* return output_simode_bld (0, operands);"
[(set_attr "cc" "clobber") [(set_attr "cc" "clobber")
(set_attr "length" "6")]) (set_attr "length" "8")])
;; ;;
;; Inverted loads with a 32bit destination. ;; Inverted loads with a 32bit destination.
;; ;;
(define_insn "" (define_insn "*extzv_1_r_inv_h8300"
[(set (match_operand:SI 0 "register_operand" "=&r") [(set (match_operand:SI 0 "register_operand" "=&r")
(zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r") (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
(match_operand:HI 3 "const_int_operand" "n")) (match_operand:HI 3 "const_int_operand" "n"))
...@@ -2440,9 +2440,9 @@ ...@@ -2440,9 +2440,9 @@
&& (1 << INTVAL (operands[2])) == INTVAL (operands[3])" && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
"* return output_simode_bld (1, operands);" "* return output_simode_bld (1, operands);"
[(set_attr "cc" "clobber") [(set_attr "cc" "clobber")
(set_attr "length" "6")]) (set_attr "length" "8")])
(define_insn "" (define_insn "*extzv_1_r_inv_h8300hs"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r") (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 3 "const_int_operand" "n")) (match_operand 3 "const_int_operand" "n"))
...@@ -2453,7 +2453,7 @@ ...@@ -2453,7 +2453,7 @@
&& (1 << INTVAL (operands[2])) == INTVAL (operands[3])" && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
"* return output_simode_bld (1, operands);" "* return output_simode_bld (1, operands);"
[(set_attr "cc" "clobber") [(set_attr "cc" "clobber")
(set_attr "length" "6")]) (set_attr "length" "8")])
(define_expand "insv" (define_expand "insv"
[(set (zero_extract:HI (match_operand:HI 0 "general_operand" "") [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
......
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