Undo most of 12/27 changes

From-SVN: r10895

gcc/config/rs6000/rs6000.c

@@ -449,69 +449,6 @@ gpc_reg_operand (op, mode)
 	  && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64));
 }
 
-/* Returns 1 if OP is register 0 or is a pseudo register.  */
-
-int
-gpc_reg0_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  && (GET_CODE (op) != REG || REGNO (op) == 0 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
-}
-
-/* Returns 1 if OP is register 3 or is a pseudo register.  */
-
-int
-gpc_reg3_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != REG || mode != GET_MODE (op))
-    return 0;			/* do not allow SUBREG's */
-
-  return (REGNO (op) == 3 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
-}
-
-/* Returns 1 if OP is register 4 or is a pseudo register.  */
-
-int
-gpc_reg4_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) != REG || mode != GET_MODE (op))
-    return 0;			/* do not allow SUBREG's */
-
-  return (REGNO (op) == 4 || REGNO (op) >= FIRST_PSEUDO_REGISTER);
-}
-
-/* Returns 1 if OP is either a pseudo-register or CR1.  */
-
-int
-cc_reg1_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  && (GET_CODE (op) != REG
-	      || REGNO (op) >= FIRST_PSEUDO_REGISTER
-	      || REGNO (op) == 69));
-}
-
-/* Returns 1 if OP is either a pseudo-register or CR0.  */
-
-int
-cc_reg0_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
-{
-  return (register_operand (op, mode)
-	  && (GET_CODE (op) != REG
-	      || REGNO (op) >= FIRST_PSEUDO_REGISTER
-	      || REGNO (op) == 68));
-}
-
 /* Returns 1 if OP is either a pseudo-register or a register denoting a
    CR field.  */
 

gcc/config/rs6000/rs6000.h

@@ -69,11 +69,11 @@ Boston, MA 02111-1307, USA.  */
 %{mcpu=rsc1: -D_ARCH_PWR} \
 %{mcpu=403: -D_ARCH_PPC} \
 %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
-%{mcpu=602: -mppc} \
-%{mcpu=603: -mppc} \
-%{mcpu=603e: -mppc} \
-%{mcpu=604: -mppc} \
-%{mcpu=620: -mppc}"
+%{mcpu=602: -d_ARCH_PPC} \
+%{mcpu=603: -D_ARCH_PPC} \
+%{mcpu=603e: -D_ARCH_PPC} \
+%{mcpu=604: -D_ARCH_PPC} \
+%{mcpu=620: -D_ARCH_PPC}"
 
 /* Define the options for the binder: Start text at 512, align all segments
    to 512 bytes, and warn if there is text relocation.
@@ -758,16 +758,11 @@ extern struct rs6000_cpu_select rs6000_select[];
    So make a class for registers valid as base registers.
 
    Also, cr0 is the only condition code register that can be used in
-   arithmetic insns, so make a separate class for it.  Common mode
-   needs to clobber cr1, so add a class for that as well.  */
+   arithmetic insns, so make a separate class for it. */
 
 enum reg_class
 {
   NO_REGS,
-  R0_REGS,
-  R3_REGS,
-  R4_REGS,
-  R34_REGS,
   BASE_REGS,
   GENERAL_REGS,
   FLOAT_REGS,
@@ -779,7 +774,6 @@ enum reg_class
   SPECIAL_REGS,
   SPEC_OR_GEN_REGS,
   CR0_REGS,
-  CR1_REGS,
   CR_REGS,
   NON_FLOAT_REGS,
   ALL_REGS,
@@ -793,10 +787,6 @@ enum reg_class
 #define REG_CLASS_NAMES							\
 {									\
   "NO_REGS",								\
-  "R0_REGS",								\
-  "R3_REGS",								\
-  "R4_REGS",								\
-  "R34_REGS",								\
   "BASE_REGS",								\
   "GENERAL_REGS",							\
   "FLOAT_REGS",								\
@@ -808,7 +798,6 @@ enum reg_class
   "SPECIAL_REGS",							\
   "SPEC_OR_GEN_REGS",							\
   "CR0_REGS",								\
-  "CR1_REGS",								\
   "CR_REGS",								\
   "NON_FLOAT_REGS",							\
   "ALL_REGS"								\
@@ -821,10 +810,6 @@ enum reg_class
 #define REG_CLASS_CONTENTS						\
 {									\
   { 0x00000000, 0x00000000, 0x00000000 },	/* NO_REGS */		\
-  { 0x00000001, 0x00000000, 0x00000000 },	/* R0_REGS */		\
-  { 0x00000008, 0x00000000, 0x00000000 },	/* R3_REGS */		\
-  { 0x00000010, 0x00000000, 0x00000000 },	/* R4_REGS */		\
-  { 0x00000018, 0x00000000, 0x00000000 },	/* R34_REGS */		\
   { 0xfffffffe, 0x00000000, 0x00000008 },	/* BASE_REGS */		\
   { 0xffffffff, 0x00000000, 0x00000008 },	/* GENERAL_REGS */	\
   { 0x00000000, 0xffffffff, 0x00000000 },	/* FLOAT_REGS */	\
@@ -836,7 +821,6 @@ enum reg_class
   { 0x00000000, 0x00000000, 0x00000007 },	/* SPECIAL_REGS */	\
   { 0xffffffff, 0x00000000, 0x0000000f },	/* SPEC_OR_GEN_REGS */	\
   { 0x00000000, 0x00000000, 0x00000010 },	/* CR0_REGS */		\
-  { 0x00000000, 0x00000000, 0x00000020 },	/* CR1_REGS */		\
   { 0x00000000, 0x00000000, 0x00000ff0 },	/* CR_REGS */		\
   { 0xffffffff, 0x00000000, 0x0000ffff },	/* NON_FLOAT_REGS */	\
   { 0xffffffff, 0xffffffff, 0x0000ffff }	/* ALL_REGS */		\
@@ -848,13 +832,10 @@ enum reg_class
    or could index an array.  */
 
 #define REGNO_REG_CLASS(REGNO)	\
- ((REGNO) == 0 ? R0_REGS	\
-  : (REGNO) == 3 ? R3_REGS	\
-  : (REGNO) == 4 ? R4_REGS	\
+ ((REGNO) == 0 ? GENERAL_REGS	\
   : (REGNO) < 32 ? BASE_REGS	\
   : FP_REGNO_P (REGNO) ? FLOAT_REGS \
   : (REGNO) == 68 ? CR0_REGS	\
-  : (REGNO) == 69 ? CR1_REGS	\
   : CR_REGNO_P (REGNO) ? CR_REGS \
   : (REGNO) == 64 ? MQ_REGS	\
   : (REGNO) == 65 ? LINK_REGS	\
@@ -875,13 +856,8 @@ enum reg_class
    : (C) == 'q' ? MQ_REGS	\
    : (C) == 'c' ? CTR_REGS	\
    : (C) == 'l' ? LINK_REGS	\
-   : (C) == 't' ? CR1_REGS	\
-   : (C) == 'u' ? R3_REGS	\
-   : (C) == 'v' ? R4_REGS	\
-   : (C) == 'w' ? R34_REGS	\
    : (C) == 'x' ? CR0_REGS	\
    : (C) == 'y' ? CR_REGS	\
-   : (C) == 'z' ? R0_REGS	\
    : NO_REGS)
 
 /* The letters I, J, K, L, M, N, and P in a register constraint string
@@ -2597,11 +2573,6 @@ do {									\
   {"u_short_cint_operand", {CONST_INT}},			\
   {"non_short_cint_operand", {CONST_INT}},			\
   {"gpc_reg_operand", {SUBREG, REG}},				\
-  {"gpc_reg0_operand", {SUBREG, REG}},				\
-  {"gpc_reg3_operand", {SUBREG, REG}},				\
-  {"gpc_reg4_operand", {SUBREG, REG}},				\
-  {"cc_reg0_operand", {SUBREG, REG}},				\
-  {"cc_reg1_operand", {SUBREG, REG}},				\
   {"cc_reg_operand", {SUBREG, REG}},				\
   {"reg_or_short_operand", {SUBREG, REG, CONST_INT}},		\
   {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}},	\
@@ -2652,12 +2623,7 @@ extern int any_operand ();
 extern int short_cint_operand ();
 extern int u_short_cint_operand ();
 extern int non_short_cint_operand ();
-extern int gpc_reg0_operand ();
-extern int gpc_reg3_operand ();
-extern int gpc_reg4_operand ();
 extern int gpc_reg_operand ();
-extern int cc_reg0_operand ();
-extern int cc_reg1_operand ();
 extern int cc_reg_operand ();
 extern int reg_or_short_operand ();
 extern int reg_or_neg_short_operand ();

gcc/config/rs6000/rs6000.md

@@ -1294,27 +1294,14 @@
     {
       emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
       emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-      emit_insn (gen_divmodsi4_common ());
+      emit_insn (gen_divss_call ());
       emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
       emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
       DONE;
     }
 }")
 
-(define_insn "divmodsi4_common"
-  [(set (reg:SI 3)
-	(div:SI (reg:SI 3) (reg:SI 4)))
-   (set (reg:SI 4)
-	(mod:SI (reg:SI 3) (reg:SI 4)))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (match_scratch:SI 1 "=z"))
-   (clobber (match_scratch:CC 2 "=x"))
-   (clobber (match_scratch:CC 3 "=t"))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __divss"
-  [(set_attr "type" "jmpreg")])
-
-(define_insn "*divmodsi4_power"
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "gpc_reg_operand" "r")))
@@ -1324,7 +1311,7 @@
   "divs %0,%1,%2"
   [(set_attr "type" "idiv")])
 
-(define_insn "*divsi3_powerpc"
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
         (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                 (match_operand:SI 2 "gpc_reg_operand" "r")))]
@@ -1343,24 +1330,13 @@
     {
       emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
       emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-      emit_insn (gen_udivsi3_common ());
+      emit_insn (gen_quous_call ());
       emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
       DONE;
     }
 }")
 
-(define_insn "udivsi3_common"
-  [(set (reg:SI 3)
-	(udiv:SI (reg:SI 3) (reg:SI 4)))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (match_scratch:SI 1 "=z"))
-   (clobber (match_scratch:CC 2 "=x"))
-   (clobber (match_scratch:CC 3 "=t"))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __quous"
-  [(set_attr "type" "jmpreg")])
-
-(define_insn "*udivsi3_powerpc"
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
         (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                  (match_operand:SI 2 "gpc_reg_operand" "r")))]
@@ -1390,21 +1366,12 @@
     {
       emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
       emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-      emit_insn (gen_divsi3_common ());
+      emit_insn (gen_quoss_call ());
       emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
       DONE;
     }
 }")
 
-(define_insn "divsi3_common"
-  [(set (reg:SI 3)
-	(div:SI (reg:SI 3) (reg:SI 4)))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (match_scratch:SI 1 "=z"))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __quoss"
-  [(set_attr "type" "jmpreg")])
-
 (define_expand "modsi3"
   [(use (match_operand:SI 0 "gpc_reg_operand" ""))
    (use (match_operand:SI 1 "gpc_reg_operand" ""))
@@ -1532,7 +1499,7 @@
       {
 	emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
 	emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-	emit_insn (gen_udivmodsi4_common ());
+	emit_insn (gen_divus_call ());
 	emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
 	emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
 	DONE;
@@ -1558,19 +1525,71 @@
   DONE;
 }")
 
-(define_insn "udivmodsi4_common"
+;; AIX architecture-independent common-mode multiply (DImode),
+;; divide/modulus, and quotient subroutine calls.  Input operands in R3 and
+;; R4; results in R3 and sometimes R4; link register always clobbered by bla
+;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
+;; assumed unused if generating common-mode, so ignore.
+(define_insn "mulh_call"
+  [(set (reg:SI 3)
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
+			       (sign_extend:DI (reg:SI 4)))
+		      (const_int 32))))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (reg:SI 4))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __mulh")
+
+(define_insn "mull_call"
+  [(set (reg:DI 3)
+	(mult:DI (sign_extend:DI (reg:SI 3))
+		 (sign_extend:DI (reg:SI 4))))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (reg:SI 0))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __mull")
+
+(define_insn "divss_call"
+  [(set (reg:SI 3)
+	(div:SI (reg:SI 3) (reg:SI 4)))
+   (set (reg:SI 4)
+	(mod:SI (reg:SI 3) (reg:SI 4)))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (reg:SI 0))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __divss")
+
+(define_insn "divus_call"
   [(set (reg:SI 3)
 	(udiv:SI (reg:SI 3) (reg:SI 4)))
    (set (reg:SI 4)
 	(umod:SI (reg:SI 3) (reg:SI 4)))
    (clobber (match_scratch:SI 0 "=l"))
-   (clobber (match_scratch:SI 1 "=z"))
-   (clobber (match_scratch:CC 2 "=x"))
-   (clobber (match_scratch:CC 3 "=t"))]
+   (clobber (reg:SI 0))
+   (clobber (match_scratch:CC 1 "=x"))
+   (clobber (reg:CC 69))]
   "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __divus"
-  [(set_attr "type" "jmpreg")])
+  "bla __divus")
 
+(define_insn "quoss_call"
+  [(set (reg:SI 3)
+	(div:SI (reg:SI 3) (reg:SI 4)))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (match_scratch:CC 1 "=x"))
+   (clobber (reg:CC 69))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __quoss")
+
+(define_insn "quous_call"
+  [(set (reg:SI 3)
+	(udiv:SI (reg:SI 3) (reg:SI 4)))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (reg:SI 0))
+   (clobber (match_scratch:CC 1 "=x"))
+   (clobber (reg:CC 69))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __quous")
 
 (define_insn "andsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
@@ -3672,10 +3691,14 @@
 {
   if (! TARGET_POWER && ! TARGET_POWERPC)
     {
+      int endian = (WORDS_BIG_ENDIAN == 0);
       emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
       emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-      emit_insn (gen_mulsidi3_common ());
-      emit_move_insn (operands[0], gen_rtx (REG, DImode, 3));
+      emit_insn (gen_mull_call ());
+      emit_move_insn (operand_subword (operands[0], endian, 0, DImode),
+		      gen_rtx (REG, SImode, 3));
+      emit_move_insn (operand_subword (operands[0], 1 - endian, 0, DImode),
+		      gen_rtx (REG, SImode, 4));
       DONE;
     }
   else if (TARGET_POWER)
@@ -3685,16 +3708,6 @@
     }
 }")
 
-(define_insn "mulsidi3_common"
-  [(set (reg:DI 3)
-	(mult:DI (sign_extend:DI (reg:SI 3))
-		 (sign_extend:DI (reg:SI 4))))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (match_scratch:SI 1 "=z"))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __mull"
-  [(set_attr "type" "jmpreg")])
-
 (define_insn "mulsidi3_mq"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
@@ -3788,7 +3801,7 @@
     {
       emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
       emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-      emit_insn (gen_smulsi3_highpart_common ());
+      emit_insn (gen_mulh_call ());
       emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
       DONE;
     }
@@ -3799,34 +3812,26 @@
     }
 }")
 
-(define_insn "smulsi3_highpart_common"
-  [(set (reg:SI 3)
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
-			       (sign_extend:DI (reg:SI 4)))
-		      (const_int 32))))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 4))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __mulh"
-  [(set_attr "type" "jmpreg")])
-
 (define_insn "smulsi3_highpart_mq"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
+	 (lshiftrt:DI (mult:DI (sign_extend:DI
+				(match_operand:SI 1 "gpc_reg_operand" "%r"))
+			       (sign_extend:DI
+				(match_operand:SI 2 "gpc_reg_operand" "r")))
 		      (const_int 32))))
    (clobber (match_scratch:SI 3 "=q"))]
   "TARGET_POWER"
   "mul %0,%1,%2"
   [(set_attr "type" "imul")])
 
-(define_insn "*smulsi3_highpart_powerpc"
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
+	 (lshiftrt:DI (mult:DI (sign_extend:DI
+				(match_operand:SI 1 "gpc_reg_operand" "%r"))
+			       (sign_extend:DI
+				(match_operand:SI 2 "gpc_reg_operand" "r")))
 		      (const_int 32))))]
   "TARGET_POWERPC"
   "mulhw %0,%1,%2"
@@ -4407,6 +4412,15 @@
   ""
   "
 {
+  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+    {
+      emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
+		      operand_subword_force (operands[1], 1, DFmode));
+      emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
+		      operand_subword_force (operands[1], 0, DFmode));
+      DONE;
+    }
+
   if (GET_CODE (operands[0]) != REG)
     operands[1] = force_reg (DFmode, operands[1]);