Fix sparc when assembler lacks support for vis3/fmaf instructions.

gcc/

	* config/sparc/sparc.h: Do not force TARGET_VIS3 and TARGET_FMAF
	to zero when assembler lacks support for such instructions.
	* config/sparc/sparc.c (sparc_option_override): Clear MASK_VIS3
	and MASK_FMAF in defaults when assembler lacks necessary support.

gcc/testsuite/

	* gcc.target/sparc/cmask.c: Remove 'vis3' target check and specify
	'-mvis3' instead of 'mcpu=niagara3' in options.
	* gcc.target/sparc/fhalve.c: Likewise.
	* gcc.target/sparc/fnegop.c: Likewise.
	* gcc.target/sparc/fpadds.c: Likewise.
	* gcc.target/sparc/fshift.c: Likewise.
	* gcc.target/sparc/fucmp.c: Likewise.
	* gcc.target/sparc/lzd.c: Likewise.
	* gcc.target/sparc/vis3misc.c: Likewise.
	* gcc.target/sparc/xmul.c: Likewise.

From-SVN: r179875

gcc/ChangeLog

+2011-10-12  David S. Miller  <davem@davemloft.net>
+
+	* config/sparc/sparc.h: Do not force TARGET_VIS3 and TARGET_FMAF
+	to zero when assembler lacks support for such instructions.
+	* config/sparc/sparc.c (sparc_option_override): Clear MASK_VIS3
+	and MASK_FMAF in defaults when assembler lacks necessary support.
+
 2011-10-12  Jakub Jelinek  <jakub@redhat.com>
 
 	* config/i386/sse.md (vec_unpacks_lo_<mode>,

gcc/config/sparc/sparc.c

@@ -850,7 +850,11 @@ sparc_option_override (void)
 
   cpu = &cpu_table[(int) sparc_cpu_and_features];
   target_flags &= ~cpu->disable;
-  target_flags |= cpu->enable;
+  target_flags |= (cpu->enable
+#ifndef HAVE_AS_FMAF_HPC_VIS3
+		   & ~(MASK_FMAF | MASK_VIS3)
+#endif
+		   );
 
   /* If -mfpu or -mno-fpu was explicitly used, don't override with
      the processor default.  */

gcc/config/sparc/sparc.h

@@ -1871,10 +1871,6 @@ extern int sparc_indent_opcode;
 
 #ifndef HAVE_AS_FMAF_HPC_VIS3
 #define AS_NIAGARA3_FLAG "b"
-#undef TARGET_FMAF
-#define TARGET_FMAF 0
-#undef TARGET_VIS3
-#define TARGET_VIS3 0
 #else
 #define AS_NIAGARA3_FLAG "d"
 #endif

gcc/testsuite/ChangeLog

+2011-10-12  David S. Miller  <davem@davemloft.net>
+
+	* gcc.target/sparc/cmask.c: Remove 'vis3' target check and specify
+	'-mvis3' instead of 'mcpu=niagara3' in options.
+	* gcc.target/sparc/fhalve.c: Likewise.
+	* gcc.target/sparc/fnegop.c: Likewise.
+	* gcc.target/sparc/fpadds.c: Likewise.
+	* gcc.target/sparc/fshift.c: Likewise.
+	* gcc.target/sparc/fucmp.c: Likewise.
+	* gcc.target/sparc/lzd.c: Likewise.
+	* gcc.target/sparc/vis3misc.c: Likewise.
+	* gcc.target/sparc/xmul.c: Likewise.
+
 2011-10-12  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gnat.dg/vect1.ad[sb]: New test.

gcc/testsuite/gcc.target/sparc/cmask.c

-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 
 void test_cm8 (long x)
 {

gcc/testsuite/gcc.target/sparc/fhalve.c

-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 
 float test_fhadds (float x, float y)
 {

gcc/testsuite/gcc.target/sparc/fnegop.c

-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-O2 -mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mvis3" } */
 
 float test_fnadds(float x, float y)
 {

gcc/testsuite/gcc.target/sparc/fpadds.c

-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef int __v1si __attribute__((vector_size(4)));
 typedef short __v4hi __attribute__((vector_size(8)));

gcc/testsuite/gcc.target/sparc/fshift.c

-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef short __v4hi __attribute__((vector_size(8)));
 

gcc/testsuite/gcc.target/sparc/fucmp.c

-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef unsigned char vec8 __attribute__((vector_size(8)));
 
 long test_fucmple8 (vec8 a, vec8 b)

gcc/testsuite/gcc.target/sparc/lzd.c

-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 int test_clz(int a)
 {
   return __builtin_clz(a);

gcc/testsuite/gcc.target/sparc/vis3misc.c

-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef int __v2si __attribute__((vector_size(8)));
 typedef short __v4hi __attribute__((vector_size(8)));
 typedef unsigned char __v8qi __attribute__((vector_size(8)));

gcc/testsuite/gcc.target/sparc/xmul.c

-/* { dg-do compile { target { vis3 } } } */
-/* { dg-options "-mcpu=niagara3 -mvis" } */
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
 typedef long long int64_t;
 
 int64_t test_umulxhi (int64_t x, int64_t y)