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lvzhengyang
riscv-gcc-1
Commits
fa6aeae1
Commit
fa6aeae1
authored
May 05, 2010
by
Maxim Kuvyrkov
Committed by
Maxim Kuvyrkov
May 05, 2010
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* doc/invoke.texi (-mfix-cortex-m3-ldrd): Move from ARC section to ARM.
From-SVN: r159073
parent
6d729f28
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gcc/ChangeLog
View file @
fa6aeae1
2010-05-05 Maxim Kuvyrkov <maxim@codesourcery.com>
* doc/invoke.texi (-mfix-cortex-m3-ldrd): Move from ARC section to ARM.
2010-05-05 Jason Merrill <jason@redhat.com>
PR c++/43787
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gcc/doc/invoke.texi
View file @
fa6aeae1
...
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@@ -9742,13 +9742,6 @@ Put functions, data, and readonly data in @var{text-section},
by default. This can be overridden with the @code{section} attribute.
@xref{Variable Attributes}.
@item -mfix-cortex-m3-ldrd
@opindex mfix-cortex-m3-ldrd
Some Cortex-M3 cores can cause data corruption when @code{ldrd} instructions
with overlapping destination and base registers are used. This option avoids
generating these instructions. This option is enabled by default when
@option{-mcpu=cortex-m3} is specified.
@end table
@node ARM Options
...
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@@ -10095,6 +10088,13 @@ This is enabled by default on targets (uClinux, SymbianOS) where the runtime
loader
imposes
this
restriction
,
and
when
@
option
{-
fpic
}
or
@
option
{-
fPIC
}
is
specified
.
@
item
-
mfix
-
cortex
-
m3
-
ldrd
@
opindex
mfix
-
cortex
-
m3
-
ldrd
Some
Cortex
-
M3
cores
can
cause
data
corruption
when
@
code
{
ldrd
}
instructions
with
overlapping
destination
and
base
registers
are
used
.
This
option
avoids
generating
these
instructions
.
This
option
is
enabled
by
default
when
@
option
{-
mcpu
=
cortex
-
m3
}
is
specified
.
@
end
table
@
node
AVR
Options
...
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