rs6000.md (movsf): Remove explicit secondary-reload-like functionality.

        * rs6000.md (movsf): Remove explicit secondary-reload-like
        functionality.  Only truncate SFmode store if in FPR.
        (movsf splitters): Combine const_double splitters.
        (movsf_hardfloat): Add GPR support.

From-SVN: r23645

gcc/ChangeLog

+Fri Nov 13 22:50:37 1998  David Edelsohn  <edelsohn@mhpcc.edu>
+
+	* rs6000.md (movsf): Remove explicit secondary-reload-like
+	functionality.  Only truncate SFmode store if in FPR.
+	(movsf splitters): Combine const_double splitters.
+	(movsf_hardfloat): Add GPR support.
+
 Fri Nov 13 11:02:11 1998  Stan Cox  <scox@cygnus.com>
 
 	* splet.h (SUBTARGET_OVERRIDE_OPTIONS): New to

gcc/config/rs6000/rs6000.md

@@ -5686,80 +5686,23 @@
       && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
     operands[1] = alter_subreg (operands[1]);
 
-  if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (SFmode, operands[1]);
-
-  else if (TARGET_HARD_FLOAT)
+  if (GET_CODE (operands[0]) == MEM)
     {
-      if (! TARGET_POWERPC64
-	  && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
+      /* If operands[1] is a register, it may have double-precision data
+	 in it, so truncate it to single precision.  We need not do
+	 this for POWERPC.  */
+      if (! TARGET_POWERPC && TARGET_HARD_FLOAT
+	  && GET_CODE (operands[1]) == REG
+	  && (FP_REGNO_P (REGNO (operands[1]))
+	      || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
 	{
-	  /* If this is a store to memory or another integer register do the
-	     move directly.  Otherwise store to a temporary stack slot and
-	     load from there into a floating point register.  */
-
-	  if (GET_CODE (operands[0]) == MEM
-	      || (GET_CODE (operands[0]) == REG
-		  && (REGNO (operands[0]) < 32
-		      || (reload_in_progress
-			  && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
-	    {
-	      emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
-			      operand_subword (operands[1], 0, 0, SFmode));
-	      DONE;
-	    }
-	  else
-	    {
-	      rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
-
-	      emit_move_insn (stack_slot, operands[1]);
-	      emit_move_insn (operands[0], stack_slot);
-	      DONE;
-	    }
+	  rtx newreg
+	    = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
+	  emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
+	  operands[1] = newreg;
 	}
 
-      if (GET_CODE (operands[0]) == MEM)
-	{
-	  /* If operands[1] is a register, it may have double-precision data
-	     in it, so truncate it to single precision.  We need not do
-	     this for POWERPC.  */
-	  if (! TARGET_POWERPC && TARGET_HARD_FLOAT
-	      && GET_CODE (operands[1]) == REG)
-	    {
-	      rtx newreg
-		= reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
-	      emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
-	      operands[1] = newreg;
-	    }
-
-	  operands[1] = force_reg (SFmode, operands[1]);
-	}
-
-      if (! TARGET_POWERPC64
-	  && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
-	{
-	  if (GET_CODE (operands[1]) == MEM
-#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
-	      || GET_CODE (operands[1]) == CONST_DOUBLE
-#endif
-	      || (GET_CODE (operands[1]) == REG
-		  && (REGNO (operands[1]) < 32
-		      || (reload_in_progress
-			  && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
-	    {
-	      emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
-			      operand_subword (operands[1], 0, 0, SFmode));
-	      DONE;
-	    }
-	  else
-	    {
-	      rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
-
-	      emit_move_insn (stack_slot, operands[1]);
-	      emit_move_insn (operands[0], stack_slot);
-	      DONE;
-	    }
-	}
+      operands[1] = force_reg (SFmode, operands[1]);
     }
 
   if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT)
@@ -5775,7 +5718,7 @@
 (define_split
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
 	(match_operand:SF 1 "const_double_operand" ""))]
-  "! TARGET_POWERPC64 && reload_completed
+  "reload_completed
    && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
 	   && GET_CODE (SUBREG_REG (operands[0])) == REG
@@ -5789,44 +5732,30 @@
   REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
   REAL_VALUE_TO_TARGET_SINGLE (rv, l);
 
-  operands[2] = operand_subword (operands[0], 0, 0, SFmode);
-  operands[3] = GEN_INT(l);
-}")
-
-(define_split
-  [(set (match_operand:SF 0 "gpc_reg_operand" "")
-	(match_operand:SF 1 "const_double_operand" ""))]
-  "TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
-       || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
-	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
-  [(set (match_dup 2) (match_dup 3))]
-  "
-{
-  long l;
-  REAL_VALUE_TYPE rv;
-
-  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
-  REAL_VALUE_TO_TARGET_SINGLE (rv, l);
+  if (! TARGET_POWERPC64)
+    operands[2] = operand_subword (operands[0], 0, 0, SFmode);
+  else
+    operands[2] = gen_lowpart (SImode, operands[0]);
 
-  operands[2] = gen_lowpart (SImode, operands[0]);
   operands[3] = GEN_INT(l);
 }")
 
 (define_insn "*movsf_hardfloat"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,!r,!r")
-	(match_operand:SF 1 "input_operand" "f,m,f,G,Fn"))]
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r")
+	(match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))]
   "(gpc_reg_operand (operands[0], SFmode)
    || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
   "@
+   mr %0,%1
+   {l%U1%X1|lwz%U1%X1} %0,%1
+   {st%U0%X0|stw%U0%X0} %1,%0
    fmr %0,%1
    lfs%U1%X1 %0,%1
    stfs%U0%X0 %1,%0
    #
    #"
-  [(set_attr "type" "fp,fpload,fpstore,*,*")
-   (set_attr "length" "4,4,4,4,8")])
+  [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*")
+   (set_attr "length" "4,4,4,4,4,4,4,8")])
 
 (define_insn "*movsf_softfloat"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")