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riscv-gcc-1
Commit f9477efd by Kazu Hirata Committed by Kazu Hirata
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h8300.c: Fix formatting. 

	* config/h8300/h8300.c: Fix formatting.
	* config/h8300/h8300.h: Likewise.

From-SVN: r49822
parent 404ae494
Showing with 36 additions and 31 deletions
gcc/ChangeLog
2002-02-17 Kazu Hirata <kazu@hxi.com>
* config/h8300/h8300.c: Fix formatting.
* config/h8300/h8300.h: Likewise.
2002-02-17 Philipp Thomas <pthomas@suse.de>
* doc/tm.texi: Explain why empty strings should not be
......
gcc/config/h8300/h8300.c
......@@ -2411,25 +2411,25 @@ get_shift_alg (shift_type, shift_mode, count, info)
}
}
else if (TARGET_H8300 && 24 <= count && count <= 28)
{
info->remainder = count - 24;
{
info->remainder = count - 24;
switch (shift_type)
{
case SHIFT_ASHIFT:
info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
info->shift1 = "shll.b\t%z0";
goto end;
case SHIFT_LSHIFTRT:
info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
info->shift1 = "shlr.b\t%w0";
switch (shift_type)
{
case SHIFT_ASHIFT:
info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
info->shift1 = "shll.b\t%z0";
goto end;
case SHIFT_LSHIFTRT:
info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
info->shift1 = "shlr.b\t%w0";
goto end;
case SHIFT_ASHIFTRT:
info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
info->shift1 = "shar.b\t%w0";
goto end;
case SHIFT_ASHIFTRT:
info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
info->shift1 = "shar.b\t%w0";
goto end;
}
}
}
}
else if ((TARGET_H8300H && count == 24)
|| (TARGET_H8300S && 24 <= count && count <= 25))
{
......
gcc/config/h8300/h8300.h
......@@ -121,7 +121,7 @@ extern int target_flags;
{"int32", 8, N_("Make integers 32 bits wide")}, \
{"addresses", 64, NULL}, \
{"quickcall", 128, \
N_("Use registers for argument passing")}, \
N_("Use registers for argument passing")}, \
{"no-quickcall", -128, \
N_("Do not use registers for argument passing")}, \
{"slowbyte", 256, \
......@@ -217,15 +217,15 @@ extern int target_flags;
See also the macro `Pmode' defined below. */
#define POINTER_SIZE (TARGET_H8300H || TARGET_H8300S ? 32 : 16)
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16)
#define LONG_TYPE_SIZE 32
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16)
#define LONG_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 32
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 32
#define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 32
#define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
#define MAX_FIXED_MODE_SIZE 32
#define MAX_FIXED_MODE_SIZE 32
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
#define PARM_BOUNDARY (TARGET_H8300H || TARGET_H8300S ? 32 : 16)
......@@ -405,11 +405,11 @@ enum reg_class {
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
#define REG_CLASS_CONTENTS \
#define REG_CLASS_CONTENTS \
{ {0}, /* No regs */ \
{0x6ff}, /* GENERAL_REGS */ \
{0x100}, /* MAC_REGS */ \
{0x7ff}, /* ALL_REGS */ \
{0x6ff}, /* GENERAL_REGS */ \
{0x100}, /* MAC_REGS */ \
{0x7ff}, /* ALL_REGS */ \
}
/* The same information, inverted:
......@@ -904,9 +904,9 @@ struct cum_arg
|| (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \
&& REG_OK_FOR_BASE_P (SUBREG_REG (X))))
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
if (RTX_OK_FOR_BASE_P (X)) goto ADDR; \
if (CONSTANT_ADDRESS_P (X)) goto ADDR; \
if (CONSTANT_ADDRESS_P (X)) goto ADDR; \
if (GET_CODE (X) == PLUS \
&& CONSTANT_ADDRESS_P (XEXP (X, 1)) \
&& RTX_OK_FOR_BASE_P (XEXP (X, 0))) goto ADDR;
......
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