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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
f8f49aea
Commit
f8f49aea
authored
Oct 14, 2008
by
Ben Elliston
Committed by
Ben Elliston
Oct 14, 2008
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* config/rs6000/rs6000.md (cell_micro): Fix formatting.
From-SVN: r141103
parent
88de9dd0
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gcc/ChangeLog
View file @
f8f49aea
2008
-
10
-
14
Ben
Elliston
<
bje
@au
.
ibm
.
com
>
*
config
/
rs6000
/
rs6000
.
md
(
cell_micro
)
:
Fix
formatting
.
2008
-
10
-
13
Joseph
Myers
<
joseph
@codesourcery
.
com
>
*
combine
.
c
(
simplify_set
)
:
Avoid
calling
LOAD_EXTEND_OP
on
...
...
gcc/config/rs6000/rs6000.md
View file @
f8f49aea
...
...
@@ -145,10 +145,9 @@
;; If this instruction is microcoded on the CELL processor
; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
(define_attr "cell_micro" "not,conditional,always"
(if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
(const_string "always")
(const_string "not")))
(if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
(const_string "always")
(const_string "not")))
(automata_option "ndfa")
...
...
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