alpha.h (TARGET_SWITCHES): Document switches.

        * alpha.h (TARGET_SWITCHES): Document switches.
        (TARGET_OPTIONS): Likewise.

From-SVN: r24626

gcc/config/alpha/alpha.h

@@ -185,26 +185,30 @@ extern enum alpha_fp_trap_mode alpha_fptm;
    where VALUE is the bits to set or minus the bits to clear.
    An empty string NAME is used to identify the default VALUE.  */
 
-#define TARGET_SWITCHES				\
-  { {"no-soft-float", MASK_FP},			\
-    {"soft-float", - MASK_FP},			\
-    {"fp-regs", MASK_FPREGS},			\
-    {"no-fp-regs", - (MASK_FP|MASK_FPREGS)},	\
-    {"alpha-as", -MASK_GAS},			\
-    {"gas", MASK_GAS},				\
-    {"ieee-conformant", MASK_IEEE_CONFORMANT},	\
-    {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT},	\
-    {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT}, \
-    {"build-constants", MASK_BUILD_CONSTANTS},  \
-    {"float-vax", MASK_FLOAT_VAX},		\
-    {"float-ieee", -MASK_FLOAT_VAX},		\
-    {"bwx", MASK_BWX},				\
-    {"no-bwx", -MASK_BWX},			\
-    {"cix", MASK_CIX},				\
-    {"no-cix", -MASK_CIX},			\
-    {"max", MASK_MAX},				\
-    {"no-max", -MASK_MAX},			\
-    {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT} }
+#define TARGET_SWITCHES							\
+  { {"no-soft-float", MASK_FP, "Use hardware fp"},			\
+    {"soft-float", - MASK_FP, "Do not use hardware fp"},		\
+    {"fp-regs", MASK_FPREGS, "Use fp registers"},			\
+    {"no-fp-regs", - (MASK_FP|MASK_FPREGS), "Do not use fp registers"},	\
+    {"alpha-as", -MASK_GAS, "Do not assume GAS"},			\
+    {"gas", MASK_GAS, "Assume GAS"},					\
+    {"ieee-conformant", MASK_IEEE_CONFORMANT,				\
+     "Request IEEE-conformant math library routines (OSF/1)"},		\
+    {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT,				\
+     "Emit IEEE-conformant code, without inexact exceptions"},		\
+    {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT,	\
+     "Emit IEEE-conformant code, with inexact exceptions"},		\
+    {"build-constants", MASK_BUILD_CONSTANTS,				\
+     "Do not emit complex integer constants to read-only memory"},	\
+    {"float-vax", MASK_FLOAT_VAX, "Use VAX fp"},			\
+    {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"},		\
+    {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"},	\
+    {"no-bwx", -MASK_BWX, ""},						\
+    {"cix", MASK_CIX, "Emit code for the counting ISA extension"},	\
+    {"no-cix", -MASK_CIX, ""},						\
+    {"max", MASK_MAX, "Emit code for the motion video ISA extension"},	\
+    {"no-max", -MASK_MAX, ""},						\
+    {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
 
 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
 
@@ -235,13 +239,18 @@ extern char *alpha_fptm_string;	/* For -mfp-trap-mode=[n|u|su|sui]  */
 extern char *alpha_tp_string;	/* For -mtrap-precision=[p|f|i] */
 extern char *alpha_mlat_string;	/* For -mmemory-latency= */
 
-#define TARGET_OPTIONS				\
-{						\
-  {"cpu=",		&alpha_cpu_string},	\
-  {"fp-rounding-mode=",	&alpha_fprm_string},	\
-  {"fp-trap-mode=",	&alpha_fptm_string},	\
-  {"trap-precision=",	&alpha_tp_string},	\
-  {"memory-latency=",	&alpha_mlat_string},	\
+#define TARGET_OPTIONS					\
+{							\
+  {"cpu=",		&alpha_cpu_string,		\
+   "Generate code for a given CPU"},			\
+  {"fp-rounding-mode=",	&alpha_fprm_string,		\
+   "Control the generated fp rounding mode"},		\
+  {"fp-trap-mode=",	&alpha_fptm_string,		\
+   "Control the IEEE trap mode"},			\
+  {"trap-precision=",	&alpha_tp_string,		\
+   "Control the precision given to fp exceptions"},	\
+  {"memory-latency=",	&alpha_mlat_string,		\
+   "Tune expected memory latency"},			\
 }
 
 /* Attempt to describe CPU characteristics to the preprocessor.  */