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lvzhengyang
riscv-gcc-1
Commits
f8411fcc
Commit
f8411fcc
authored
Jul 02, 2013
by
Ian Bolton
Committed by
Ian Bolton
Jul 02, 2013
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AArch64 - Update insv tests for big endian
From-SVN: r200597
parent
26366d28
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4 changed files
with
103 additions
and
1 deletions
+103
-1
gcc/testsuite/ChangeLog
+7
-0
gcc/testsuite/gcc.target/aarch64/insv_1.c
+2
-1
gcc/testsuite/gcc.target/aarch64/insv_2.c
+85
-0
gcc/testsuite/lib/target-supports.exp
+9
-0
No files found.
gcc/testsuite/ChangeLog
View file @
f8411fcc
2013-07-02 Ian Bolton <ian.bolton@arm.com>
* gcc.target/config/aarch64/insv_1.c: Update to show it doesn't work
on big endian.
* gcc.target/config/aarch64/insv_2.c: New test for big endian.
* lib/target-supports.exp: Define aarch64_little_endian.
2013-07-02 Ian Bolton <ian.bolton@arm.com>
* gcc.target/aarch64/abs_1.c: New test.
2013-07-02 Ian Bolton <ian.bolton@arm.com>
...
...
gcc/testsuite/gcc.target/aarch64/insv_1.c
View file @
f8411fcc
/* { dg-do run } */
/* { dg-do run
{ target aarch64*-*-* }
} */
/* { dg-options "-O2 --save-temps -fno-inline" } */
/* { dg-require-effective-target aarch64_little_endian } */
extern
void
abort
(
void
);
...
...
gcc/testsuite/gcc.target/aarch64/insv_2.c
0 → 100644
View file @
f8411fcc
/* { dg-do run { target aarch64*-*-* } } */
/* { dg-options "-O2 --save-temps -fno-inline" } */
/* { dg-require-effective-target aarch64_big_endian } */
extern
void
abort
(
void
);
typedef
struct
bitfield
{
unsigned
short
eight
:
8
;
unsigned
short
four
:
4
;
unsigned
short
five
:
5
;
unsigned
short
seven
:
7
;
unsigned
int
sixteen
:
16
;
}
bitfield
;
bitfield
bfi1
(
bitfield
a
)
{
/* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 56, 8" } } */
a
.
eight
=
3
;
return
a
;
}
bitfield
bfi2
(
bitfield
a
)
{
/* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 43, 5" } } */
a
.
five
=
7
;
return
a
;
}
bitfield
movk
(
bitfield
a
)
{
/* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 16" } } */
a
.
sixteen
=
7531
;
return
a
;
}
bitfield
set1
(
bitfield
a
)
{
/* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 272678883688448" } } */
a
.
five
=
0x1f
;
return
a
;
}
bitfield
set0
(
bitfield
a
)
{
/* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -272678883688449" } } */
a
.
five
=
0
;
return
a
;
}
int
main
(
int
argc
,
char
**
argv
)
{
static
bitfield
a
;
bitfield
b
=
bfi1
(
a
);
bitfield
c
=
bfi2
(
b
);
bitfield
d
=
movk
(
c
);
if
(
d
.
eight
!=
3
)
abort
();
if
(
d
.
five
!=
7
)
abort
();
if
(
d
.
sixteen
!=
7531
)
abort
();
d
=
set1
(
d
);
if
(
d
.
five
!=
0x1f
)
abort
();
d
=
set0
(
d
);
if
(
d
.
five
!=
0
)
abort
();
return
0
;
}
/* { dg-final { cleanup-saved-temps } } */
gcc/testsuite/lib/target-supports.exp
View file @
f8411fcc
...
...
@@ -2106,6 +2106,15 @@ proc check_effective_target_aarch64_big_endian { } {
}]
}
# Return 1 if this is a AArch64 target supporting little endian
proc check_effective_target_aarch64_little_endian { } {
return [check_no_compiler_messages aarch64_little_endian assembly {
#if !defined(__aarch64__) || defined(__AARCH64EB__)
#error FOO
#endif
}]
}
# Return 1 is this is an arm target using 32-bit instructions
proc check_effective_target_arm32 { } {
return [check_no_compiler_messages arm32 assembly {
...
...
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