sparc.c (sparc_operand, [...]): Recognize CONSTANT_P_RTX.

	* sparc.c (sparc_operand, move_operand,	arith_operand,
	arith11_operand, arith10_operand, arith_double_operand,
	arith11_double_operand, arith10_double_operand, small_int,
	uns_small_int): Recognize CONSTANT_P_RTX.
	(output_sized_memop, output_move_with_extension,
	output_load_address, output_size_for_block_move,
	output_block_move, delay_operand): Remove, has not been
	enabled or referenced for years.
	* sparc.md (movstrsi, block_move_insn): Likewise.
	* sparc.h (PREDICATE_CODES): Define.
	* linux-aout.h (MACHINE_STATE_{SAVE,RESTORE}): Override with
	version which uses getcc/setcc traps to save/restore condition
	codes.
	* linux64.h: Likewise.
	* sunos4.h: Likewise.
	* linux.h: Likewise.
	* sol2.h: Likewise.
	* sun4o3.h: Likewise.

From-SVN: r20917

gcc/ChangeLog

+Fri Jul  3 02:33:35 1998  David S. Miller  <davem@pierdol.cobaltmicro.com>
+
+	* sparc.c (sparc_operand, move_operand,	arith_operand,
+	arith11_operand, arith10_operand, arith_double_operand,
+	arith11_double_operand, arith10_double_operand, small_int,
+	uns_small_int): Recognize CONSTANT_P_RTX.
+	(output_sized_memop, output_move_with_extension,
+	output_load_address, output_size_for_block_move,
+	output_block_move, delay_operand): Remove, has not been
+	enabled or referenced for years.
+	* sparc.md (movstrsi, block_move_insn): Likewise.
+	* sparc.h (PREDICATE_CODES): Define.
+	* linux-aout.h (MACHINE_STATE_{SAVE,RESTORE}): Override with
+	version which uses getcc/setcc traps to save/restore condition
+	codes.
+	* linux64.h: Likewise.
+	* sunos4.h: Likewise.
+	* linux.h: Likewise.
+	* sol2.h: Likewise.
+	* sun4o3.h: Likewise.
+
 Fri Jul  3 02:28:05 1998  Richard Henderson  <rth@cygnus.com>
 
 	* alpha.c (alpha_initialize_trampoline): Hack around Pmode/ptr_mode

gcc/config/sparc/linux-aout.h

@@ -109,3 +109,22 @@ Boston, MA 02111-1307, USA.  */
    long double yet.  */
 #define LONG_DOUBLE_TYPE_SIZE 128
 #endif
+
+/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
+   traps available which can get and set the condition codes
+   reliably.  */
+#undef MACHINE_STATE_SAVE
+#define MACHINE_STATE_SAVE(ID)				\
+  unsigned long int ms_flags, ms_saveret;		\
+  asm volatile("ta	0x20\n\t"			\
+	       "mov	%%g1, %0\n\t"			\
+	       "mov	%%g2, %1\n\t"			\
+	       : "=r" (ms_flags), "=r" (ms_saveret));
+
+#undef MACHINE_STATE_RESTORE
+#define MACHINE_STATE_RESTORE(ID)			\
+  asm volatile("mov	%0, %%g1\n\t"			\
+	       "mov	%1, %%g2\n\t"			\
+	       "ta	0x21\n\t"			\
+	       : /* no outputs */			\
+	       : "r" (ms_flags), "r" (ms_saveret));

gcc/config/sparc/linux.h

@@ -238,3 +238,22 @@ do {									\
    long double yet.  */
 #define LONG_DOUBLE_TYPE_SIZE 128
 #endif
+
+/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
+   traps available which can get and set the condition codes
+   reliably.  */
+#undef MACHINE_STATE_SAVE
+#define MACHINE_STATE_SAVE(ID)				\
+  unsigned long int ms_flags, ms_saveret;		\
+  asm volatile("ta	0x20\n\t"			\
+	       "mov	%%g1, %0\n\t"			\
+	       "mov	%%g2, %1\n\t"			\
+	       : "=r" (ms_flags), "=r" (ms_saveret));
+
+#undef MACHINE_STATE_RESTORE
+#define MACHINE_STATE_RESTORE(ID)			\
+  asm volatile("mov	%0, %%g1\n\t"			\
+	       "mov	%1, %%g2\n\t"			\
+	       "ta	0x21\n\t"			\
+	       : /* no outputs */			\
+	       : "r" (ms_flags), "r" (ms_saveret));

gcc/config/sparc/linux64.h

@@ -224,3 +224,22 @@ do {									\
    RELATIVE relocations.  */
 
 /* #define DWARF_OFFSET_SIZE PTR_SIZE */
+
+/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
+   traps available which can get and set the condition codes
+   reliably.  */
+#undef MACHINE_STATE_SAVE
+#define MACHINE_STATE_SAVE(ID)				\
+  unsigned long int ms_flags, ms_saveret;		\
+  asm volatile("ta	0x20\n\t"			\
+	       "mov	%%g1, %0\n\t"			\
+	       "mov	%%g2, %1\n\t"			\
+	       : "=r" (ms_flags), "=r" (ms_saveret));
+
+#undef MACHINE_STATE_RESTORE
+#define MACHINE_STATE_RESTORE(ID)			\
+  asm volatile("mov	%0, %%g1\n\t"			\
+	       "mov	%1, %%g2\n\t"			\
+	       "ta	0x21\n\t"			\
+	       : /* no outputs */			\
+	       : "r" (ms_flags), "r" (ms_saveret));

gcc/config/sparc/sol2.h

@@ -210,4 +210,23 @@ Boston, MA 02111-1307, USA.  */
    sparc_override_options will disable V8+ if not generating V9 code.  */
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_V8PLUS)
+
+/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
+   traps available which can get and set the condition codes
+   reliably.  */
+#undef MACHINE_STATE_SAVE
+#define MACHINE_STATE_SAVE(ID)				\
+  unsigned long int ms_flags, ms_saveret;		\
+  asm volatile("ta	0x20\n\t"			\
+	       "mov	%%g1, %0\n\t"			\
+	       "mov	%%g2, %1\n\t"			\
+	       : "=r" (ms_flags), "=r" (ms_saveret));
+
+#undef MACHINE_STATE_RESTORE
+#define MACHINE_STATE_RESTORE(ID)			\
+  asm volatile("mov	%0, %%g1\n\t"			\
+	       "mov	%1, %%g2\n\t"			\
+	       "ta	0x21\n\t"			\
+	       : /* no outputs */			\
+	       : "r" (ms_flags), "r" (ms_saveret));
 

gcc/config/sparc/sparc.h

@@ -3186,6 +3186,49 @@ do {									\
     }								\
 }
 
+/* Define the codes that are matched by predicates in sparc.c.  */
+
+#define PREDICATE_CODES								    \
+{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},			    \
+{"fp_zero_operand", {CONST_DOUBLE}},						    \
+{"intreg_operand", {SUBREG, REG}},						    \
+{"fcc_reg_operand", {REG}},							    \
+{"icc_or_fcc_reg_operand", {REG}},						    \
+{"restore_operand", {REG}},							    \
+{"call_operand", {MEM}},							    \
+{"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, ADDRESSOF,    \
+                          SUBREG, REG, PLUS, LO_SUM, CONST_INT}},		    \
+{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE}},		    \
+{"symbolic_memory_operand", {SUBREG, MEM}},					    \
+{"label_ref_operand", {LABEL_REF}},						    \
+{"sp64_medium_pic_operand", {CONST}},						    \
+{"data_segment_operand", {SYMBOL_REF, PLUS, CONST}},				    \
+{"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}},			    \
+{"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}},				    \
+{"sparc_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, MEM}},		    \
+{"move_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE, MEM}},	    \
+{"splittable_symbolic_memory_operand", {MEM}},					    \
+{"splittable_immediate_memory_operand", {MEM}},					    \
+{"eq_or_neq", {EQ, NE}},							    \
+{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}},				    \
+{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}},		    \
+{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}},					    \
+{"v8plus_regcmp_op", {EQ, NE}},							    \
+{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}},					    \
+{"cc_arithop", {AND, IOR, XOR}},						    \
+{"cc_arithopn", {AND, IOR}},							    \
+{"arith_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}},			    \
+{"arith11_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}},			    \
+{"arith10_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}},			    \
+{"arith_double_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}},   \
+{"arith11_double_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}}, \
+{"arith10_double_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}}, \
+{"small_int", {CONST_INT, CONSTANT_P_RTX}},					    \
+{"uns_small_int", {CONST_INT, CONSTANT_P_RTX}},					    \
+{"uns_arith_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},		    \
+{"clobbered_register", {REG}},
+
+
 /* The number of Pmode words for the setjmp buffer.  */
 #define JMP_BUF_SIZE 12
 

gcc/config/sparc/sparc.md

@@ -2314,55 +2314,6 @@
 ;; ??? There's no symbolic (set (mem:DI ...) ...).
 ;; Experimentation with v9 suggested one isn't needed.
 
-;; Block move insns.
-
-;; ??? We get better code without it.  See output_block_move in sparc.c.
-
-;; The definition of this insn does not really explain what it does,
-;; but it should suffice
-;; that anything generated as this insn will be recognized as one
-;; and that it will not successfully combine with anything.
-;(define_expand "movstrsi"
-;  [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
-;		   (mem:BLK (match_operand:BLK 1 "general_operand" "")))
-;	      (use (match_operand:SI 2 "nonmemory_operand" ""))
-;	      (use (match_operand:SI 3 "immediate_operand" ""))
-;	      (clobber (match_dup 0))
-;	      (clobber (match_dup 1))
-;	      (clobber (match_scratch:SI 4 ""))
-;	      (clobber (reg:SI 100))
-;	      (clobber (reg:SI 1))])]
-;  ""
-;  "
-;{
-;  /* If the size isn't known, don't emit inline code.  output_block_move
-;     would output code that's much slower than the library function.
-;     Also don't output code for large blocks.  */
-;  if (GET_CODE (operands[2]) != CONST_INT
-;      || GET_CODE (operands[3]) != CONST_INT
-;      || INTVAL (operands[2]) / INTVAL (operands[3]) > 16)
-;    FAIL;
-;
-;  operands[0] = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
-;  operands[1] = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
-;  operands[2] = force_not_mem (operands[2]);
-;}")
-
-;(define_insn "*block_move_insn"
-;  [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r"))
-;	(mem:BLK (match_operand:SI 1 "register_operand" "+r")))
-;   (use (match_operand:SI 2 "nonmemory_operand" "rn"))
-;   (use (match_operand:SI 3 "immediate_operand" "i"))
-;   (clobber (match_dup 0))
-;   (clobber (match_dup 1))
-;   (clobber (match_scratch:SI 4 "=&r"))
-;   (clobber (reg:SI 100))
-;   (clobber (reg:SI 1))]
-;  ""
-;  "* return output_block_move (operands);"
-;  [(set_attr "type" "multi")
-;   (set_attr "length" "6")])
-
 ;; Floating point move insns
 
 ;; This pattern forces (set (reg:SF ...) (const_double ...))

gcc/config/sparc/sun4o3.h

@@ -5,6 +5,25 @@
   fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall .mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \
 	   (LABELNO), (LABELNO))
 
-/* LINK_SPEC is needed only for Sunos 4.  */
+/* LINK_SPEC is needed only for SunOS 4.  */
 
 #undef LINK_SPEC
+
+/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
+   traps available which can get and set the condition codes
+   reliably.  */
+#undef MACHINE_STATE_SAVE
+#define MACHINE_STATE_SAVE(ID)				\
+  unsigned long int ms_flags, ms_saveret;		\
+  asm volatile("ta	0x20\n\t"			\
+	       "mov	%%g1, %0\n\t"			\
+	       "mov	%%g2, %1\n\t"			\
+	       : "=r" (ms_flags), "=r" (ms_saveret));
+
+#undef MACHINE_STATE_RESTORE
+#define MACHINE_STATE_RESTORE(ID)			\
+  asm volatile("mov	%0, %%g1\n\t"			\
+	       "mov	%1, %%g2\n\t"			\
+	       "ta	0x21\n\t"			\
+	       : /* no outputs */			\
+	       : "r" (ms_flags), "r" (ms_saveret));

gcc/config/sparc/sunos4.h

@@ -28,3 +28,22 @@ Boston, MA 02111-1307, USA.  */
 
 /* The Sun as doesn't like unaligned data.  */
 #define DWARF2_UNWIND_INFO 0
+
+/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
+   traps available which can get and set the condition codes
+   reliably.  */
+#undef MACHINE_STATE_SAVE
+#define MACHINE_STATE_SAVE(ID)				\
+  unsigned long int ms_flags, ms_saveret;		\
+  asm volatile("ta	0x20\n\t"			\
+	       "mov	%%g1, %0\n\t"			\
+	       "mov	%%g2, %1\n\t"			\
+	       : "=r" (ms_flags), "=r" (ms_saveret));
+
+#undef MACHINE_STATE_RESTORE
+#define MACHINE_STATE_RESTORE(ID)			\
+  asm volatile("mov	%0, %%g1\n\t"			\
+	       "mov	%1, %%g2\n\t"			\
+	       "ta	0x21\n\t"			\
+	       : /* no outputs */			\
+	       : "r" (ms_flags), "r" (ms_saveret));