re PR c/8281 ([Sparc] ICE when compiling with -O2 -fPIC for Ultrasparc)

	PR c/8281
	* config/sparc/sparc.md (movdi_insn_sp32_v9): Remove 'f-f' alternative.
	(movdi reg/reg split): Match only on sparc32, and v9 when int regs.

From-SVN: r64957

gcc/ChangeLog

+2003-03-28  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	PR c/8281
+	* config/sparc/sparc.md (movdi_insn_sp32_v9): Remove 'f-f' alternative.
+	(movdi reg/reg split): Match only on sparc32, and v9 when int regs.
+
 2003-03-28  Alan Modra  <amodra@bigpond.net.au>
 
 	* config/alpha/elf.h (ASM_OUTPUT_ALIGNED_BSS): Remove unnecessary

gcc/config/sparc/sparc.md

@@ -2062,9 +2062,9 @@
 
 (define_insn "*movdi_insn_sp32_v9"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-					"=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f,?e,?e,?W")
+					"=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W")
         (match_operand:DI 1 "input_operand"
-					" J,J,U,T,r,o,i,r, f, T, o, f, f, e, W, e"))]
+					" J,J,U,T,r,o,i,r, f, T, o, f, e, W, e"))]
   "! TARGET_ARCH64 && TARGET_V9
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "@
@@ -2080,13 +2080,12 @@
    ldd\t%1, %0
    #
    #
-   #
    fmovd\\t%1, %0
    ldd\\t%1, %0
    std\\t%1, %0"
-  [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*,fpmove,fpload,fpstore")
-   (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2,*,*,*")
-   (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
+  [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore")
+   (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*")
+   (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
 
 (define_insn "*movdi_insn_sp32"
   [(set (match_operand:DI 0 "nonimmediate_operand"
@@ -2425,7 +2424,14 @@
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
         (match_operand:DI 1 "register_operand" ""))]
-  "! TARGET_ARCH64 && reload_completed"
+  "reload_completed
+   && (! TARGET_V9
+       || (! TARGET_ARCH64
+           && ((GET_CODE (operands[0]) == REG
+                && REGNO (operands[0]) < 32)
+               || (GET_CODE (operands[0]) == SUBREG
+                   && GET_CODE (SUBREG_REG (operands[0])) == REG
+                   && REGNO (SUBREG_REG (operands[0])) < 32))))"
   [(clobber (const_int 0))]
 {
   rtx set_dest = operands[0];

gcc/testsuite/ChangeLog

+2003-03-28  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* gcc.dg/ultrasp7.c: New test.
+
 2003-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 
 	PR c++/10047

gcc/testsuite/gcc.dg/ultrasp7.c

+/* PR c/8281 */
+/* Originator: TANIGUCHI Yasuaki <yasuaki@k8.dion.ne.jp> */
+/* { dg-do compile { target sparc-*-* } } */
+/* { dg-options "-O2 -mcpu=ultrasparc -fPIC" } */
+
+static const double bp = 1.0, dp_l[] = { 0.0 };
+
+double __ieee754_pow(double x, double y)
+{
+  union {
+    int lo;
+    double d;
+  }uz;
+
+  double y1,t1,p_h,t,z;
+  double z_h,z_l,p_l;
+  double t2,r,s,u,v,w;
+  int i = 0;
+ 
+  double s_h,t_h;
+  double s2,s_l,t_l;
+ 
+ 
+  v = 1.0/(v+bp);
+  uz.d = s_h = s = u*v;
+  uz.lo = 0;
+  s_h = uz.d;
+  uz.d = t_h;
+  uz.lo = 3;
+  t_h = uz.d;
+  s_l = v*((u-s_h*t_h)-s_h*t_l);
+  s2 = s*s;
+  r = s2* s2* (1.1+s2*(1.2+s2*(1.3+s2*(1.4+s2*(1.5+s2*1.6)))));
+  s2 = s_h*s_h;
+  uz.lo = 0;
+  t_h = uz.d;
+  t_l = r-((t_h-3.0)-s2);
+  v = s_l*t_h+t_l*s;
+  p_l = v-(p_h-u);
+  z_h = bp *p_h;
+  z_l = bp*p_h+p_l*1.0+dp_l[i];
+  t = (double)i;
+  t1 = (((bp+z_l)+bp)+t);
+  t2 = z_l-(((t1-t)-bp)-z_h);
+  p_l = (y-y1)*t1+y*t2;
+  z = p_l+p_h;
+
+  return s*z;
+}