re PR target/19511 (ICE in in reload_cse_simplify_operands, at postreload.c:391)

        PR target/19511
        * config/i386/i386.c (ix86_preferred_reload_class): Return a proper
        subclass of the input class.
        (ix86_secondary_memory_needed): Always true for cross-MMX classes.
        Always true for cross-SSE1 classes.  Rationalize conditionals.
        * config/i386/i386.h (SSE_CLASS_P, MMX_CLASS_P): Use straight equality.
        * config/i386/i386.md (movsi_1): Add MMX/SSE zeros.  Fix alternatives
        for SSE1.  Don't check TARGET_INTER_UNIT_MOVES.
        (movdi_2): Add MMX/SSE zeros.
        (movdi_1_rex64): Likewise.  Don't check TARGET_INTER_UNIT_MOVES.
        (movsf_1): Don't check TARGET_INTER_UNIT_MOVES.
        (zero_extendsidi2_32, zero_extendsidi2_rex64): Likewise.
        (movsi_1_nointernunit, movdi_1_rex64_nointerunit): Remove.
        (movsf_1_nointerunit, zero_extendsidi2_32_1): Remove.
        (zero_extendsidi2_rex64_1): Remove.
        (MOV0 peephole): Check GENERAL_REG_P.

From-SVN: r93948

gcc/ChangeLog

 2005-01-19  Richard Henderson  <rth@redhat.com>
 
+	PR target/19511
+	* config/i386/i386.c (ix86_preferred_reload_class): Return a proper
+	subclass of the input class.
+	(ix86_secondary_memory_needed): Always true for cross-MMX classes.
+	Always true for cross-SSE1 classes.  Rationalize conditionals.
+	* config/i386/i386.h (SSE_CLASS_P, MMX_CLASS_P): Use straight equality.
+	* config/i386/i386.md (movsi_1): Add MMX/SSE zeros.  Fix alternatives
+	for SSE1.  Don't check TARGET_INTER_UNIT_MOVES.
+	(movdi_2): Add MMX/SSE zeros.
+	(movdi_1_rex64): Likewise.  Don't check TARGET_INTER_UNIT_MOVES.
+	(movsf_1): Don't check TARGET_INTER_UNIT_MOVES.
+	(zero_extendsidi2_32, zero_extendsidi2_rex64): Likewise.
+	(movsi_1_nointernunit, movdi_1_rex64_nointerunit): Remove.
+	(movsf_1_nointerunit, zero_extendsidi2_32_1): Remove.
+	(zero_extendsidi2_rex64_1): Remove.
+	(MOV0 peephole): Check GENERAL_REG_P.
+
+2005-01-19  Richard Henderson  <rth@redhat.com>
+
 	PR target/19427
 	* config/i386/i386.c (ix86_expand_vector_set): Fix third and fourth
 	shufps elements.

gcc/config/i386/i386.c

@@ -14599,6 +14599,8 @@ ix86_free_from_memory (enum machine_mode mode)
 enum reg_class
 ix86_preferred_reload_class (rtx x, enum reg_class class)
 {
+  if (class == NO_REGS)
+    return NO_REGS;
   if (GET_CODE (x) == CONST_VECTOR && x != CONST0_RTX (GET_MODE (x)))
     return NO_REGS;
   if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
@@ -14618,7 +14620,7 @@ ix86_preferred_reload_class (rtx x, enum reg_class class)
 	}
       /* General regs can load everything.  */
       if (reg_class_subset_p (class, GENERAL_REGS))
-	return GENERAL_REGS;
+	return class;
       /* In case we haven't resolved FLOAT or SSE yet, give up.  */
       if (MAYBE_FLOAT_CLASS_P (class) || MAYBE_SSE_CLASS_P (class))
 	return NO_REGS;
@@ -14640,6 +14642,7 @@ ix86_preferred_reload_class (rtx x, enum reg_class class)
 
    When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
    enforce these sanity checks.  */
+
 int
 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
 			      enum machine_mode mode, int strict)
@@ -14653,21 +14656,50 @@ ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
     {
       if (strict)
 	abort ();
-      else
-	return 1;
+      return true;
     }
-  return (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2)
-	  || ((SSE_CLASS_P (class1) != SSE_CLASS_P (class2)
-	       || MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
-	      && ((mode != SImode && (mode != DImode || !TARGET_64BIT))
-		  || (!TARGET_INTER_UNIT_MOVES && !optimize_size))));
+
+  if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
+    return true;
+
+  /* ??? This is a lie.  We do have moves between mmx/general, and for
+     mmx/sse2.  But by saying we need secondary memory we discourage the
+     register allocator from using the mmx registers unless needed.  */
+  if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
+    return true;
+
+  if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
+    {
+      /* SSE1 doesn't have any direct moves from other classes.  */
+      if (!TARGET_SSE2)
+	return true;
+
+      /* If the target says that inter-unit moves are more expensive 
+	 than moving through memory, then don't generate them.  */
+      if (!TARGET_INTER_UNIT_MOVES && !optimize_size)
+	return true;
+
+      /* Between SSE and general, we have moves no larger than word size.  */
+      if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+	return true;
+
+      /* ??? For the cost of one register reformat penalty, we could use
+	 the same instructions to move SFmode and DFmode data, but the 
+	 relevant move patterns don't support those alternatives.  */
+      if (mode == SFmode || mode == DFmode)
+	return true;
+    }
+
+  return false;
 }
+
 /* Return the cost of moving data from a register in class CLASS1 to
    one in class CLASS2.
 
    It is not required that the cost always equal 2 when FROM is the same as TO;
    on some machines it is expensive to move between registers if they are not
    general registers.  */
+
 int
 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
 			 enum reg_class class2)

gcc/config/i386/i386.h

@@ -1307,9 +1307,9 @@ enum reg_class
 #define FLOAT_CLASS_P(CLASS) \
   reg_class_subset_p ((CLASS), FLOAT_REGS)
 #define SSE_CLASS_P(CLASS) \
-  reg_class_subset_p ((CLASS), SSE_REGS)
+  ((CLASS) == SSE_REGS)
 #define MMX_CLASS_P(CLASS) \
-  reg_class_subset_p ((CLASS), MMX_REGS)
+  ((CLASS) == MMX_REGS)
 #define MAYBE_INTEGER_CLASS_P(CLASS) \
   reg_classes_intersect_p ((CLASS), GENERAL_REGS)
 #define MAYBE_FLOAT_CLASS_P(CLASS) \