Skip to content

R
riscv-gcc-1
Commit f6ee577c by Adrian Straetling Committed by Ulrich Weigand
Options

s390.md: ("hc"): New mode attribute. 

2005-05-09  Adrian Straetling  <straetling@de.ibm.com>

	* config/s390/s390.md: ("hc"): New mode attribute.
	("extendhidi2", "extendqidi2"): Merge.
	("*extendhidi2", "*extendqidi2"): Merge.
	("extendhisi2", "extendqisi2"): Merge.
	("zero_extendhidi2", "zero_extendqidi2"): Merge.
	("*zero_extendhidi2", "*zero_extendqidi2"): Merge.
	Merged 2 define_split.
	("*zero_extendhisi2", "*zero_extendqisi2"): Merge.
	("*zero_extendhisi2_64", "*zero_extendqisi2_64"): Merge.

From-SVN: r99453
parent fa77b251
Showing with 55 additions and 144 deletions
gcc/ChangeLog
2005-05-09 Adrian Straetling <straetling@de.ibm.com> 2005-05-09 Adrian Straetling <straetling@de.ibm.com>
* config/s390/s390.md: ("hc"): New mode attribute.
("extendhidi2", "extendqidi2"): Merge.
("*extendhidi2", "*extendqidi2"): Merge.
("extendhisi2", "extendqisi2"): Merge.
("zero_extendhidi2", "zero_extendqidi2"): Merge.
("*zero_extendhidi2", "*zero_extendqidi2"): Merge.
Merged 2 define_split.
("*zero_extendhisi2", "*zero_extendqisi2"): Merge.
("*zero_extendhisi2_64", "*zero_extendqisi2_64"): Merge.
2005-05-09 Adrian Straetling <straetling@de.ibm.com>
* config/s390/s390.md: ("COMPARE"): New mode macro. * config/s390/s390.md: ("COMPARE"): New mode macro.
("beq", "bne", "bgt", "bgtu", "blt", "bltu", "bge", "bgeu", ("beq", "bne", "bgt", "bgtu", "blt", "bltu", "bge", "bgeu",
"ble", "bleu", "bunordered", "bordered", "buneq", "bunlt", "ble", "bleu", "bunordered", "bordered", "buneq", "bunlt",
......
gcc/config/s390/s390.md
...@@ -264,6 +264,10 @@ ...@@ -264,6 +264,10 @@
;; of a SImode register. ;; of a SImode register.
(define_mode_attr icm_lo [(HI "3") (QI "1")]) (define_mode_attr icm_lo [(HI "3") (QI "1")])
;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
;; HImode and "llgc" in QImode.
(define_mode_attr hc [(HI "h") (QI "c")])
;; Maximum unsigned integer that fits in MODE. ;; Maximum unsigned integer that fits in MODE.
(define_mode_attr max_uint [(HI "65535") (QI "255")]) (define_mode_attr max_uint [(HI "65535") (QI "255")])
...@@ -2366,27 +2370,29 @@ ...@@ -2366,27 +2370,29 @@
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
; ;
; extendhidi2 instruction pattern(s). ; extend(hi|qi)di2 instruction pattern(s).
; ;
(define_expand "extendhidi2" (define_expand "extend<mode>di2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:HI 1 "register_operand" "")))] (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
"" ""
" "
{ {
if (!TARGET_64BIT) if (!TARGET_64BIT)
{ {
rtx tmp = gen_reg_rtx (SImode); rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_extendhisi2 (tmp, operands[1])); emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
emit_insn (gen_extendsidi2 (operands[0], tmp)); emit_insn (gen_extendsidi2 (operands[0], tmp));
DONE; DONE;
} }
else else
{ {
rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
GET_MODE_BITSIZE (<MODE>mode));
operands[1] = gen_lowpart (DImode, operands[1]); operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
DONE; DONE;
} }
} }
...@@ -2399,33 +2405,6 @@ ...@@ -2399,33 +2405,6 @@
"lgh\t%0,%1" "lgh\t%0,%1"
[(set_attr "op_type" "RXY")]) [(set_attr "op_type" "RXY")])
;
; extendqidi2 instruction pattern(s).
;
(define_expand "extendqidi2"
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
""
"
{
if (!TARGET_64BIT)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_extendqisi2 (tmp, operands[1]));
emit_insn (gen_extendsidi2 (operands[0], tmp));
DONE;
}
else
{
operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
DONE;
}
}
")
(define_insn "*extendqidi2" (define_insn "*extendqidi2"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
...@@ -2449,18 +2428,20 @@ ...@@ -2449,18 +2428,20 @@
"") "")
; ;
; extendhisi2 instruction pattern(s). ; extend(hi|qi)si2 instruction pattern(s).
; ;
(define_expand "extendhisi2" (define_expand "extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:HI 1 "register_operand" "")))] (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
"" ""
" "
{ {
rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
GET_MODE_BITSIZE(<MODE>mode));
operands[1] = gen_lowpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
DONE; DONE;
} }
") ")
...@@ -2474,23 +2455,6 @@ ...@@ -2474,23 +2455,6 @@
lhy\t%0,%1" lhy\t%0,%1"
[(set_attr "op_type" "RX,RXY")]) [(set_attr "op_type" "RX,RXY")])
;
; extendqisi2 instruction pattern(s).
;
(define_expand "extendqisi2"
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
""
"
{
operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
DONE;
}
")
(define_insn "*extendqisi2" (define_insn "*extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
...@@ -2548,37 +2512,39 @@ ...@@ -2548,37 +2512,39 @@
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
; ;
; zero_extendhidi2 instruction pattern(s). ; zero_extend(hi|qi)di2 instruction pattern(s).
; ;
(define_expand "zero_extendhidi2" (define_expand "zero_extend<mode>di2"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (match_operand:HI 1 "register_operand" "")))] (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
"" ""
" "
{ {
if (!TARGET_64BIT) if (!TARGET_64BIT)
{ {
rtx tmp = gen_reg_rtx (SImode); rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
DONE; DONE;
} }
else else
{ {
rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
GET_MODE_BITSIZE(<MODE>mode));
operands[1] = gen_lowpart (DImode, operands[1]); operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
DONE; DONE;
} }
} }
") ")
(define_insn "*zero_extendhidi2" (define_insn "*zero_extend<mode>di2"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
"TARGET_64BIT" "TARGET_64BIT"
"llgh\t%0,%1" "llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY")]) [(set_attr "op_type" "RXY")])
; ;
...@@ -2616,17 +2582,6 @@ ...@@ -2616,17 +2582,6 @@
llgt\t%0,%1" llgt\t%0,%1"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXE")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "")
(const_int 2147483647)))
(clobber (reg:CC 33))]
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(and:SI (match_dup 1)
(const_int 2147483647)))]
"")
(define_insn "*llgt_didi" (define_insn "*llgt_didi"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
...@@ -2638,71 +2593,38 @@ ...@@ -2638,71 +2593,38 @@
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXE")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:GPR 0 "register_operand" "")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "") (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
(const_int 2147483647))) (const_int 2147483647)))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_64BIT && reload_completed" "TARGET_64BIT && reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
(and:DI (match_dup 1) (and:GPR (match_dup 1)
(const_int 2147483647)))] (const_int 2147483647)))]
"") "")
; ;
; zero_extendqidi2 instruction pattern(s) ; zero_extend(hi|qi)si2 instruction pattern(s).
;
(define_expand "zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
""
"
{
if (!TARGET_64BIT)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
DONE;
}
else
{
operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
DONE;
}
}
")
(define_insn "*zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\t%0,%1"
[(set_attr "op_type" "RXY")])
;
; zero_extendhisi2 instruction pattern(s).
; ;
(define_expand "zero_extendhisi2" (define_expand "zero_extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:HI 1 "register_operand" "")))] (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
"" ""
" "
{ {
operands[1] = gen_lowpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); emit_insn (gen_andsi3 (operands[0], operands[1],
GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
DONE; DONE;
} }
") ")
(define_insn "*zero_extendhisi2_64" (define_insn "*zero_extend<mode>si2_64"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
"TARGET_ZARCH" "TARGET_ZARCH"
"llgh\t%0,%1" "llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY")]) [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendhisi2_31" (define_insn_and_split "*zero_extendhisi2_31"
...@@ -2718,29 +2640,6 @@ ...@@ -2718,29 +2640,6 @@
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"operands[2] = gen_lowpart (HImode, operands[0]);") "operands[2] = gen_lowpart (HImode, operands[0]);")
;
; zero_extendqisi2 instruction pattern(s).
;
(define_expand "zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
""
"
{
operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
DONE;
}
")
(define_insn "*zero_extendqisi2_64"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_ZARCH"
"llgc\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqisi2_31" (define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d") [(set (match_operand:SI 0 "register_operand" "=&d")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment