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riscv-gcc-1
Commit f6a1e430 by Adam Nemet Committed by Adam Nemet
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* config/mips/mips.md (*zero_extend<GPR:mode>_trunc<SHORT:mode>, 

	*zero_extendhi_truncqi):  Move after the zero_extend patterns.
	(*extenddi_truncate<mode>, *extendsi_truncate<mode>): Move after the
	extend patterns.

From-SVN: r147673
parent 6a90d232
Showing with 69 additions and 62 deletions
gcc/ChangeLog
2009-05-18 Adam Nemet <anemet@caviumnetworks.com>
* config/mips/mips.md (*zero_extend<GPR:mode>_trunc<SHORT:mode>,
*zero_extendhi_truncqi): Move after the zero_extend patterns.
(*extenddi_truncate<mode>, *extendsi_truncate<mode>): Move after the
extend patterns.
2009-05-18 H.J. Lu <hongjiu.lu@intel.com> 2009-05-18 H.J. Lu <hongjiu.lu@intel.com>
PR target/39942 PR target/39942
......
gcc/config/mips/mips.md
...@@ -2736,68 +2736,6 @@ ...@@ -2736,68 +2736,6 @@
"exts\t%0,%1,%2,31" "exts\t%0,%1,%2,31"
[(set_attr "type" "arith") [(set_attr "type" "arith")
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
;; Combiner patterns for truncate/sign_extend combinations. The SI versions
;; use the shift/truncate patterns above.
(define_insn_and_split "*extenddi_truncate<mode>"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI
(truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"#"
"&& reload_completed"
[(set (match_dup 2)
(ashift:DI (match_dup 1)
(match_dup 3)))
(set (match_dup 0)
(ashiftrt:DI (match_dup 2)
(match_dup 3)))]
{
operands[2] = gen_lowpart (DImode, operands[0]);
operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
})
(define_insn_and_split "*extendsi_truncate<mode>"
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI
(truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"#"
"&& reload_completed"
[(set (match_dup 2)
(ashift:DI (match_dup 1)
(match_dup 3)))
(set (match_dup 0)
(truncate:SI (ashiftrt:DI (match_dup 2)
(match_dup 3))))]
{
operands[2] = gen_lowpart (DImode, operands[0]);
operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
})
;; Combiner patterns to optimize truncate/zero_extend combinations.
(define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extend:GPR
(truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
{
operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
return "andi\t%0,%1,%x2";
}
[(set_attr "type" "logical")
(set_attr "mode" "<GPR:MODE>")])
(define_insn "*zero_extendhi_truncqi"
[(set (match_operand:HI 0 "register_operand" "=d")
(zero_extend:HI
(truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
[(set_attr "type" "logical")
(set_attr "mode" "HI")])
;; ;;
;; .................... ;; ....................
...@@ -2922,6 +2860,29 @@ ...@@ -2922,6 +2860,29 @@
"lbu\t%0,%1" "lbu\t%0,%1"
[(set_attr "move_type" "load") [(set_attr "move_type" "load")
(set_attr "mode" "HI")]) (set_attr "mode" "HI")])
;; Combiner patterns to optimize truncate/zero_extend combinations.
(define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extend:GPR
(truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
{
operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
return "andi\t%0,%1,%x2";
}
[(set_attr "type" "logical")
(set_attr "mode" "<GPR:MODE>")])
(define_insn "*zero_extendhi_truncqi"
[(set (match_operand:HI 0 "register_operand" "=d")
(zero_extend:HI
(truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
[(set_attr "type" "logical")
(set_attr "mode" "HI")])
;; ;;
;; .................... ;; ....................
...@@ -3048,6 +3009,45 @@ ...@@ -3048,6 +3009,45 @@
[(set_attr "move_type" "signext,load") [(set_attr "move_type" "signext,load")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
;; Combiner patterns for truncate/sign_extend combinations. The SI versions
;; use the shift/truncate patterns.
(define_insn_and_split "*extenddi_truncate<mode>"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI
(truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"#"
"&& reload_completed"
[(set (match_dup 2)
(ashift:DI (match_dup 1)
(match_dup 3)))
(set (match_dup 0)
(ashiftrt:DI (match_dup 2)
(match_dup 3)))]
{
operands[2] = gen_lowpart (DImode, operands[0]);
operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
})
(define_insn_and_split "*extendsi_truncate<mode>"
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI
(truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"#"
"&& reload_completed"
[(set (match_dup 2)
(ashift:DI (match_dup 1)
(match_dup 3)))
(set (match_dup 0)
(truncate:SI (ashiftrt:DI (match_dup 2)
(match_dup 3))))]
{
operands[2] = gen_lowpart (DImode, operands[0]);
operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
})
(define_insn "extendsfdf2" (define_insn "extendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(float_extend:DF (match_operand:SF 1 "register_operand" "f")))] (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
......
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