PR tree-optimization/94574 - aarch64: ICE during GIMPLE pass:ccp

In this PR the testcase ICEs because a BIT_INSERT_EXPR whose replaced bits are
not fully inside the container is generated. A size check is added to avoid
this kind of ICE.

gcc/ChangeLog:

	PR tree-optimization/94574
	* tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
	whether a vector-insert is rewritable using a BIT_INSERT_EXPR.

gcc/testsuite/ChangeLog:

	PR tree-optimization/94574
	* gcc.dg/pr94574.c: New test.

gcc/ChangeLog

+2020-04-14  Yang Yang <yangyang305@huawei.com>
+
+	PR tree-optimization/94574
+	* tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
+	whether a vector-insert is rewritable using a BIT_INSERT_EXPR.
+
 2020-04-14  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/94561

gcc/testsuite/ChangeLog

+2020-04-14  Yang Yang <yangyang305@huawei.com>
+
+	PR tree-optimization/94574
+	* gcc.dg/pr94574.c: New test.
+
 2020-04-14  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/94561

gcc/testsuite/gcc.dg/pr94574.c

+/* { dg-do compile } */
+/* { dg-options "-O2 -w -Wno-psabi" } */
+
+typedef unsigned int v4si __attribute__((vector_size(16)));
+typedef unsigned int v2si __attribute__((vector_size(8)));
+
+/* The aliasing is somewhat dubious here, but it must compile.  */
+
+v2si
+foo (v4si v)
+{
+  v2si res;
+  *(v4si *) &res = v;
+  return res;
+}

gcc/tree-ssa.c

@@ -1543,7 +1543,9 @@ non_rewritable_lvalue_p (tree lhs)
 	  && known_gt (wi::to_poly_offset (TYPE_SIZE_UNIT (TREE_TYPE (decl))),
 		       mem_ref_offset (lhs))
 	  && multiple_of_p (sizetype, TREE_OPERAND (lhs, 1),
-			    TYPE_SIZE_UNIT (TREE_TYPE (lhs))))
+			    TYPE_SIZE_UNIT (TREE_TYPE (lhs)))
+	  && known_ge (wi::to_poly_offset (TYPE_SIZE (TREE_TYPE (decl))),
+		       wi::to_poly_offset (TYPE_SIZE (TREE_TYPE (lhs)))))
 	{
 	  poly_uint64 lhs_bits, nelts;
 	  if (poly_int_tree_p (TYPE_SIZE (TREE_TYPE (lhs)), &lhs_bits)