Commit f62a2af5 by Chung-Ju Wu Committed by Chung-Ju Wu

[NDS32] Support [$ra + $rb << 3] form for load/store address.

gcc/
	* config/nds32/nds32.c (nds32_legitimate_index_p): Modify condition
	for load/store addressing form.
	(nds32_print_operand_address): Likewise.

From-SVN: r259201
parent e0617fb6
2018-04-07 Chung-Ju Wu <jasonwucj@gmail.com>
* config/nds32/nds32.c (nds32_legitimate_index_p): Modify condition
for load/store addressing form.
(nds32_print_operand_address): Likewise.
2018-04-06 Eric Botcazou <ebotcazou@adacore.com> 2018-04-06 Eric Botcazou <ebotcazou@adacore.com>
PR target/85196 PR target/85196
......
...@@ -1246,9 +1246,10 @@ nds32_legitimate_index_p (machine_mode outer_mode, ...@@ -1246,9 +1246,10 @@ nds32_legitimate_index_p (machine_mode outer_mode,
int multiplier; int multiplier;
multiplier = INTVAL (op1); multiplier = INTVAL (op1);
/* We only allow (mult reg const_int_1) /* We only allow (mult reg const_int_1), (mult reg const_int_2),
or (mult reg const_int_2) or (mult reg const_int_4). */ (mult reg const_int_4) or (mult reg const_int_8). */
if (multiplier != 1 && multiplier != 2 && multiplier != 4) if (multiplier != 1 && multiplier != 2
&& multiplier != 4 && multiplier != 8)
return false; return false;
regno = REGNO (op0); regno = REGNO (op0);
...@@ -1273,8 +1274,9 @@ nds32_legitimate_index_p (machine_mode outer_mode, ...@@ -1273,8 +1274,9 @@ nds32_legitimate_index_p (machine_mode outer_mode,
sv = INTVAL (op1); sv = INTVAL (op1);
/* We only allow (ashift reg const_int_0) /* We only allow (ashift reg const_int_0)
or (ashift reg const_int_1) or (ashift reg const_int_2). */ or (ashift reg const_int_1) or (ashift reg const_int_2) or
if (sv != 0 && sv != 1 && sv !=2) (ashift reg const_int_3). */
if (sv != 0 && sv != 1 && sv !=2 && sv != 3)
return false; return false;
regno = REGNO (op0); regno = REGNO (op0);
...@@ -2926,6 +2928,8 @@ nds32_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x) ...@@ -2926,6 +2928,8 @@ nds32_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x)
sv = 1; sv = 1;
else if (INTVAL (XEXP (op0, 1)) == 4) else if (INTVAL (XEXP (op0, 1)) == 4)
sv = 2; sv = 2;
else if (INTVAL (XEXP (op0, 1)) == 8)
sv = 3;
else else
gcc_unreachable (); gcc_unreachable ();
......
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