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riscv-gcc-1
Commit f5a1b0d2 by Nick Clifton
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Apply ARM/Linux patches. 

Rework cpu/architecture command line parsing.

From-SVN: r25380
parent 956662b2
Showing with 242 additions and 146 deletions
gcc/ChangeLog
1999-02-22 Nick Clifton <nickc@cygnus.com>
* config/arm/arm.h: Add TARGET_CPU_strongarm1100.
Add -mno-sched command line switch to disable scheduling of
instructions into the function's prologue.
(enum processor_type): Remove.
(TARGET_OPTIONS): Add "fpe=" option to match documentation.
(struct arm_cpu_select): Replace 'set_tune_p' and 'set_arch_p'
fields with 'processors' field.
(CONDITIONAL_REGISTER_USAGE): Allow r10 to be used if stack
checking is not enabled.
(RETURN_IN_MEMORY): Always call arm_return_in_memory.
* config/arm/arm.c: (arm_cpu): Remove.
(tune_flags): Remove.
(arm_is_strong): New variable: true iff the target processor is a
StrongARM.
(arm_is_6_or_7): New variable: true iff the target processor is an
ARM6 or and ARM7.
(arm_select): Fields reorganised.
(struct processors): processor_type field removed.
(all_procs): Remove.
(all_cores): New array: Definitions of all known ARM cpu cores.
(all_architectures): New array: Definitions of all known ARM
architectures.
(streq): New macro.
(FL_SCHED): New processor flag: processor required load
scheduling.
(FL_STRONG): New processor flag: processor is a StrongARM.
(arm_override_options): Reorganised to make code clearer.
(use_return_insn): Test for "not (TARGET_APCS and
frame_pointer_needed)".
(arm_return_in_memory): Improve handling of structures.
* config/arm/arm.md: Remove "cpu" attribute. Replace with
"is_strongarm" and "is_arm_6_or_7" attributes.
(zero_extendhisi2): Check for TARGET_SHORT_BY_BYTES before
arm_arch4.
(extendhisi2): Check for TARGET_SHORT_BY_BYTES before arm_arch4.
* invoke.texi (ARM Options): Document -mtune= and -mfp= options.
1999-02-22 Philip Blundell <philb@gnu.org>
* config/arm/linux-gas.h (INITIALIZE_TRAMPOLINE): Replace default
definition with one including cache synchronisation.
(CLEAR_INSN_CACHE): Correct syscall number and enable definition.
Move definition of inhibit_libc to...
* config/arm/xm-linux.h: ... here.
* config/arm/t-linux: Disable multilib configurations since the
only effect for most people is to cause builds to fail.
* config/arm/elf.h (ASM_FILE_START): Add .file directive.
(ASM_SPEC): Translate -mapcs-float to -mfloat for the assembler.
* config/arm/linux-elf.h (DEFAULT_VTABLE_THUNKS): Define.
(HANDLE_SYSV_PRAGMA): Likewise.
(LIB_SPEC): Copy definition from generic Linux files.
(LIBGCC_SPEC): Include -lfloat if -msoft-float was given.
(FP_DEFAULT): Set to SOFT3 on 32-bit targets.
(DWARF2_DEBUGGING_INFO): Define.
(PREFERRED_DEBUGGING_TYPE): Define as DBX_DEBUG.
Mon Feb 22 16:54:18 EST 1999 Andrew MacLeod <amacleod@cygnus.com>
* loop.c (libcall_other_regs): Make extern.
......
gcc/config/arm/arm.h
/* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
/* Definitions of target machine for GNU compiler, for ARM.
Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
and Martin Simmons (@harleqn.co.uk).
......@@ -53,6 +53,7 @@ Boston, MA 02111-1307, USA. */
#define TARGET_CPU_arm810 0x0020
#define TARGET_CPU_strongarm 0x0040
#define TARGET_CPU_strongarm110 0x0040
#define TARGET_CPU_strongarm1100 0x0040
#define TARGET_CPU_arm9 0x0080
#define TARGET_CPU_arm9tdmi 0x0080
/* Configure didn't specify */
......@@ -146,6 +147,7 @@ Unrecognized value in TARGET_CPU_DEFAULT.
%{march=arm9tdmi:-D__ARM_ARCH_4T__} \
%{march=strongarm:-D__ARM_ARCH_4__} \
%{march=strongarm110:-D__ARM_ARCH_4__} \
%{march=strongarm1100:-D__ARM_ARCH_4__} \
%{march=armv2:-D__ARM_ARCH_2__} \
%{march=armv2a:-D__ARM_ARCH_2__} \
%{march=armv3:-D__ARM_ARCH_3__} \
......@@ -175,6 +177,7 @@ Unrecognized value in TARGET_CPU_DEFAULT.
%{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
%{mcpu=strongarm:-D__ARM_ARCH_4__} \
%{mcpu=strongarm110:-D__ARM_ARCH_4__} \
%{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
%{!mcpu*:%{!m6:%{!m2:%{!m3:%(cpp_cpu_arch_default)}}}}} \
"
......@@ -258,7 +261,7 @@ Unrecognized value in TARGET_CPU_DEFAULT.
extern int target_flags;
/* The floating point instruction architecture, can be 2 or 3 */
extern char *target_fp_name;
extern char * target_fp_name;
/* Nonzero if the function prologue (and epilogue) should obey
the ARM Procedure Call Standard. */
......@@ -318,6 +321,9 @@ extern char *target_fp_name;
big-endian (for backwards compatibility with older versions of GCC). */
#define ARM_FLAG_LITTLE_WORDS (0x2000)
/* Nonzero if we need to protect the prolog from scheduling */
#define ARM_FLAG_NO_SCHED_PRO (0x4000)
/* Nonzero if a call to abort should be generated if a noreturn
function tries to return. */
#define ARM_FLAG_ABORT_NORETURN (0x8000)
......@@ -337,6 +343,7 @@ function tries to return. */
#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
#define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
#define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
#define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
#define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
/* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
......@@ -391,68 +398,39 @@ function tries to return. */
{"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
"Generate a call to abort if a noreturn function returns"}, \
{"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
{"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
"Do not move instructions into a function's prologue" }, \
{"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
SUBTARGET_SWITCHES \
{"", TARGET_DEFAULT } \
}
#define TARGET_OPTIONS \
{ \
{"cpu=", \
&arm_select[1].string, \
"Specify the name of the target CPU"}, \
{"arch=", \
&arm_select[2].string, \
"Specify the name of the target architecture"}, \
{"tune=", \
&arm_select[3].string, \
"Order instructions for best performance on this CPU"}, \
{"fp=", \
&target_fp_name, \
"Specify the version of the floating point emulator"}, \
{"structure-size-boundary=", \
&structure_size_string, \
"Specify the minumum bit alignment of structures"} \
{"cpu=", & arm_select[0].string, \
"Specify the name of the target CPU" }, \
{"arch=", & arm_select[1].string, \
"Specify the name of the target architecture" }, \
{"tune=", & arm_select[2].string, "" }, \
{"fpe=", & target_fp_name, "" }, \
{"fp=", & target_fp_name, \
"Specify the version of the floating point emulator" }, \
{ "structure-size-boundary=", & structure_size_string, \
"Specify the minumum bit alignment of structures" } \
}
/* arm_select[0] is reserved for the default cpu. */
struct arm_cpu_select
{
char *string;
char *name;
int set_tune_p;
int set_arch_p;
char * string;
char * name;
struct processors * processors;
};
/* This is a magic array. If the user specifies a command line switch
which matches one of the entries in TARGET_OPTIONS then the corresponding
string pointer will be set to the value specified by the user. */
extern struct arm_cpu_select arm_select[];
#ifndef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_ARM2
#endif
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT ((char *) 0)
#endif
/* Which processor we are running on, for instruction scheduling
purposes. */
enum processor_type
{
PROCESSOR_ARM2,
PROCESSOR_ARM3,
PROCESSOR_ARM6,
PROCESSOR_ARM7,
PROCESSOR_ARM8,
PROCESSOR_ARM9,
PROCESSOR_STARM,
PROCESSOR_NONE /* NOTE: This must be last, since it doesn't
appear in the attr_cpu list */
};
/* Recast the cpu class to be the cpu attribute. */
#define arm_cpu_attr ((enum attr_cpu)arm_cpu)
extern enum processor_type arm_cpu;
enum prog_mode_type
{
prog_mode26,
......@@ -493,6 +471,15 @@ extern int arm_fast_multiply;
/* Nonzero if this chip supports the ARM Architecture 4 extensions */
extern int arm_arch4;
/* Nonzero if this chip can benefit from load scheduling. */
extern int arm_ld_sched;
/* Nonzero if this chip is a StrongARM. */
extern int arm_is_strong;
/* Nonzero if this chip is a an ARM6 or an ARM7. */
extern int arm_is_6_or_7;
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#endif
......@@ -634,8 +621,8 @@ extern char * structure_size_string;
r4-r8 S register variable
r9 S (rfp) register variable (real frame pointer)
r10 F S (sl) stack limit (not currently used)
r10 F S (sl) stack limit (used by -mapcs-stack-check)
r11 F S (fp) argument pointer
r12 (ip) temp workspace
r13 F S (sp) lower end of current stack frame
......@@ -730,6 +717,11 @@ extern char * structure_size_string;
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
} \
else if (! TARGET_APCS_STACK) \
{ \
fixed_regs[10] = 0; \
call_used_regs[10] = 0; \
} \
}
/* Return number of consecutive hard regs needed starting at reg REGNO
......@@ -1062,9 +1054,7 @@ do { \
/* How large values are returned */
/* A C expression which can inhibit the returning of certain function values
in registers, based on the type of value. */
#define RETURN_IN_MEMORY(TYPE) \
(TYPE_MODE ((TYPE)) == BLKmode || \
(AGGREGATE_TYPE_P ((TYPE)) && arm_return_in_memory ((TYPE))))
#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
values must be in memory. On the ARM, they need only do so if larger
......@@ -1779,8 +1769,8 @@ extern int arm_pic_register;
#define FINALIZE_PIC arm_finalize_pic ()
/* We can't directly access anything that contains a symbol, nor can
we indirect via the constant pool */
/* We can't directly access anything that contains a symbol,
nor can we indirect via the constant pool. */
#define LEGITIMATE_PIC_OPERAND_P(X) \
(! symbol_mentioned_p (X) \
&& (! CONSTANT_POOL_ADDRESS_P (X) \
......
gcc/config/arm/arm.md
......@@ -45,10 +45,7 @@
; by the -mapcs-{32,26} flag, and possibly the -mcpu=... option.
(define_attr "prog_mode" "prog26,prog32" (const (symbol_ref "arm_prog_mode")))
; CPU attribute is used to determine the best instruction mix for performance
; on the named processor.
(define_attr "cpu" "arm2,arm3,arm6,arm7,arm8,arm9,st_arm"
(const (symbol_ref "arm_cpu_attr")))
(define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_is_strong")))
; Floating Point Unit. If we only have floating point emulation, then there
; is no point in scheduling the floating point insns. (Well, for best
......@@ -100,11 +97,9 @@
"normal,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4"
(const_string "normal"))
; Load scheduling, set from the cpu characteristic
(define_attr "ldsched" "no,yes"
(if_then_else (eq_attr "cpu" "arm8,arm9,st_arm")
(const_string "yes")
(const_string "no")))
; Load scheduling, set from the arm_ld_sched variable
; initialised by arm_override_options()
(define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
; condition codes: this one is used by final_prescan_insn to speed up
; conditionalizing instructions. It saves having to scan the rtl to see if
......@@ -137,10 +132,7 @@
; have one. Later ones, such as StrongARM, have write-back caches, so don't
; suffer blockages enough to warrent modelling this (and it can adversely
; affect the schedule).
(define_attr "model_wbuf" "no,yes"
(if_then_else (eq_attr "cpu" "arm6,arm7")
(const_string "yes")
(const_string "no")))
(define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_is_6_or_7")))
(define_attr "write_conflict" "no,yes"
(if_then_else (eq_attr "type"
......@@ -267,13 +259,15 @@
(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_mem_r")) 7 7)
(define_function_unit "core" 1 0
(and (eq_attr "cpu" "!arm8,st_arm") (eq_attr "type" "mult")) 16 16)
(and (eq_attr "ldsched" "no") (eq_attr "type" "mult")) 16 16)
(define_function_unit "core" 1 0
(and (eq_attr "cpu" "arm8") (eq_attr "type" "mult")) 4 4)
(and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "no"))
(eq_attr "type" "mult")) 4 4)
(define_function_unit "core" 1 0
(and (eq_attr "cpu" "st_arm") (eq_attr "type" "mult")) 3 2)
(and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "yes"))
(eq_attr "type" "mult")) 3 2)
(define_function_unit "core" 1 0 (eq_attr "type" "store2") 3 3)
......@@ -1209,7 +1203,7 @@
(const_int 0)))
(clobber (match_scratch:QI 3 "=r"))]
"INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) > 0
&& (INTVAL (operands[2]) + INTVAL (operands[1]) <= 8)"
&& ((INTVAL (operands[2]) + INTVAL (operands[1])) <= 8)"
"*
operands[1] = GEN_INT (((1 << INTVAL (operands[1])) - 1)
<< INTVAL (operands[2]));
......@@ -1287,7 +1281,7 @@
emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width)));
emit_insn (gen_iorsi3 (op1, gen_rtx_LSHIFTRT (SImode, operands[0],
operands[1]),
operands[1]),
op0));
emit_insn (gen_rotlsi3 (subtarget, op1, operands[1]));
}
......@@ -2173,16 +2167,20 @@
""
"
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
if (GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_ZERO_EXTEND (SImode, operands[1])));
DONE;
}
if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_movhi_bytes (operands[0], operands[1]));
DONE;
if (TARGET_SHORT_BY_BYTES)
{
emit_insn (gen_movhi_bytes (operands[0], operands[1]));
DONE;
}
else if (arm_arch4)
{
emit_insn (gen_rtx_SET (VOIDmode,
operands[0],
gen_rtx_ZERO_EXTEND (SImode, operands[1])));
DONE;
}
}
if (! s_register_operand (operands[1], HImode))
operands[1] = copy_to_mode_reg (HImode, operands[1]);
......@@ -2274,19 +2272,21 @@
(const_int 16)))]
""
"
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_SIGN_EXTEND (SImode, operands[1])));
DONE;
}
if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
{
if (GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
DONE;
}
if (TARGET_SHORT_BY_BYTES)
{
emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
DONE;
}
else if (arm_arch4)
{
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_SIGN_EXTEND (SImode, operands[1])));
DONE;
}
}
if (! s_register_operand (operands[1], HImode))
operands[1] = copy_to_mode_reg (HImode, operands[1]);
operands[1] = gen_lowpart (SImode, operands[1]);
......@@ -2381,7 +2381,8 @@
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
emit_insn (gen_rtx_SET (VOIDmode,
operands[0],
gen_rtx_SIGN_EXTEND (HImode, operands[1])));
DONE;
}
......@@ -2437,8 +2438,8 @@
&& GET_CODE (XEXP (operands[1], 1)) != CONST_INT
&& ! s_register_operand (XEXP (operands[1], 1), VOIDmode))
operands[1] = gen_rtx_PLUS (GET_MODE (operands[1]),
XEXP (operands[1], 1),
XEXP (operands[1], 0));
XEXP (operands[1], 1),
XEXP (operands[1], 0));
}
")
......@@ -2454,7 +2455,8 @@
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
emit_insn (gen_rtx_SET (VOIDmode,
operands[0],
gen_rtx_SIGN_EXTEND (SImode, operands[1])));
DONE;
}
......@@ -2508,8 +2510,8 @@
&& GET_CODE (XEXP (operands[1], 1)) != CONST_INT
&& ! s_register_operand (XEXP (operands[1], 1), VOIDmode))
operands[1] = gen_rtx_PLUS (GET_MODE (operands[1]),
XEXP (operands[1], 1),
XEXP (operands[1], 0));
XEXP (operands[1], 1),
XEXP (operands[1], 0));
}
")
......@@ -3260,7 +3262,7 @@
XEXP (XEXP (operands[0], 0), 1)));
emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (DFmode, operands[2]),
operands[1]));
operands[1]));
if (code == POST_DEC)
emit_insn (gen_addsi3 (operands[2], operands[2], GEN_INT (-8)));
......@@ -4184,10 +4186,10 @@
extern int arm_ccfsm_state;
if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2)
{
arm_ccfsm_state += 2;
return \"\";
}
{
arm_ccfsm_state += 2;
return \"\";
}
return \"b%?\\t%l0\";
}")
......@@ -6136,7 +6138,6 @@
}
")
;; The next two patterns occur when an AND operation is followed by a
;; scc insn sequence
......
gcc/config/arm/elf.h
/* Definitions of target machine for GNU compiler,
for ARM with ELF obj format.
Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
Copyright (C) 1995, 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
Contributed by Philip Blundell <philb@gnu.org> and
Catherine Moore <clm@cygnus.com>
......@@ -100,7 +100,7 @@ Boston, MA 02111-1307, USA. */
by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */
#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \
do { \
char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
char * name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \
&& ! AT_END && TOP_LEVEL \
&& DECL_INITIAL (DECL) == error_mark_node \
......@@ -143,7 +143,7 @@ do { \
#ifndef ASM_SPEC
#define ASM_SPEC "%{mbig-endian:-EB} %{mcpu=*:-m%*} %{march=*:-m%*} \
%{mapcs-*:-mapcs-%*} %{mthumb-interwork:-mthumb-interwork}"
%{mapcs-*:-mapcs-%*} %{mthumb-interwork:-mthumb-interwork} %{mapcs-float:mfloat}"
#endif
#ifndef LINK_SPEC
......@@ -198,9 +198,10 @@ arm_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
#ifndef ASM_FILE_START
#define ASM_FILE_START(STREAM) \
do { \
extern char *version_string; \
extern char * version_string; \
fprintf (STREAM, "%s Generated by gcc %s for ARM/elf\n", \
ASM_COMMENT_START, version_string); \
output_file_directive ((STREAM), main_input_filename); \
} while (0)
#endif
......@@ -209,7 +210,7 @@ do { \
#define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
do \
{ \
char *s = (char *) alloca (40 + strlen (PREFIX)); \
char * s = (char *) alloca (40 + strlen (PREFIX)); \
extern int arm_target_label, arm_ccfsm_state; \
extern rtx arm_target_insn; \
\
......@@ -332,6 +333,3 @@ do { \
fputc ('\n', FILE); } while (0)
#include "arm/aout.h"
gcc/config/arm/linux-elf.h
......@@ -34,8 +34,20 @@ Boston, MA 02111-1307, USA. */
" %{mapcs-26:-mapcs-26} %(!mapcs-26:-mapcs-32}"
#endif
/* This was defined in linux.h. Define it here also. */
#undef DEFAULT_VTABLE_THUNKS
#define DEFAULT_VTABLE_THUNKS 1
/* Handle #pragma weak and #pragma pack. */
#define HANDLE_SYSV_PRAGMA
/* Now we define the strings used to build the spec file. */
#define LIB_SPEC "%{!shared:%{!symbolic:-lc}}"
#define LIB_SPEC \
"%{shared: -lc} \
%{!shared: %{pthread:-lpthread} \
%{profile:-lc_p} %{!profile: -lc}}"
#define LIBGCC_SPEC "%{msoft-float:-lfloat} -lgcc"
/* Add the compiler's crtend, and the library's crtn. */
#define ENDFILE_SPEC "%{!shared:crtend.o%s} %{shared:crtendS.o%s} \
......@@ -64,6 +76,10 @@ Boston, MA 02111-1307, USA. */
#ifndef SUBTARGET_DEFAULT_APCS26
#undef CPP_APCS_PC_DEFAULT_SPEC
#define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_32__"
/* On 32-bit machine it is always safe to assume we have the "new"
floating point system. */
#undef FP_DEFAULT
#define FP_DEFAULT FP_SOFT3
#endif
/* Allow #sccs in preprocessor. */
......@@ -201,5 +217,10 @@ const_section () \
assemble_name (FILE, NAME2); \
fputc ('\n', FILE); } while (0)
/* Make DWARF2 an option, but keep DBX as the default for now.
Use -gdwarf2 to turn on DWARF2. */
#define DWARF2_DEBUGGING_INFO
#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
#include "arm/elf.h"
#include "arm/linux-gas.h"
gcc/config/arm/linux-gas.h
/* Definitions of target machine for GNU compiler.
ARM Linux-based GNU systems version.
Copyright (C) 1997, 1998 Free Software Foundation, Inc.
Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
Contributed by Russell King <rmk92@ecs.soton.ac.uk>.
This file is part of GNU CC.
......@@ -59,29 +59,25 @@ Boston, MA 02111-1307, USA. */
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE BITS_PER_WORD
#if 0 /* not yet */
/* Emit code to set up a trampoline and synchronise the caches. */
#undef INITIALIZE_TRAMPOLINE
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
(CXT)); \
emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
(FNADDR)); \
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
0, VOIDmode, 2, TRAMP, Pmode, \
plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
}
/* Clear the instruction cache from `beg' to `end'. This makes an
inline system call to SYS_cacheflush. The arguments are as
follows:
cacheflush (start, end, flags)
*/
inline system call to SYS_cacheflush. */
#define CLEAR_INSN_CACHE(BEG, END) \
{ \
register unsigned long _beg __asm ("a1") = (unsigned long) (BEG); \
register unsigned long _end __asm ("a2") = (unsigned long) (END); \
register unsigned long _flg __asm ("a3") = 0; \
__asm __volatile ("swi 0x9000b8"); \
__asm __volatile ("swi 0x9f0002"); \
}
#endif
/* If cross-compiling, don't require stdio.h etc to build libgcc.a. */
#ifdef CROSS_COMPILE
#ifndef inhibit_libc
#define inhibit_libc
#endif
#endif
gcc/config/arm/t-arm-elf
......@@ -23,9 +23,11 @@ dp-bit.c: $(srcdir)/config/fp-bit.c
echo '#endif' >> dp-bit.c
cat $(srcdir)/config/fp-bit.c >> dp-bit.c
MULTILIB_OPTIONS = mlittle-endian/mbig-endian mhard-float/msoft-float mapcs-32/mapcs-26 fno-leading-underscore/fleading-underscore
MULTILIB_DIRNAMES = le be fpu soft 32bit 26bit elf under
MULTILIB_MATCHES =
# MULTILIB_OPTIONS = mlittle-endian/mbig-endian mhard-float/msoft-float mapcs-32/mapcs-26 fno-leading-underscore/fleading-underscore
# MULTILIB_DIRNAMES = le be fpu soft 32bit 26bit elf under
# MULTILIB_MATCHES =
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
# LIBGCC = stmp-multilib
# INSTALL_LIBGCC = install-multilib
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc
gcc/config/arm/t-linux
......@@ -13,8 +13,10 @@ LIBGCC1 = libgcc1-asm.a
LIB1ASMSRC = arm/lib1funcs.asm
LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx
MULTILIB_OPTIONS = mapcs-32
MULTILIB_DIRNAMES = apcs-32
# If you want to build both APCS variants as multilib options this is how
# to do it.
#MULTILIB_OPTIONS = mapcs-32/apcs-26
#MULTILIB_DIRNAMES = apcs-32 apcs-26
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
gcc/invoke.texi
......@@ -170,7 +170,7 @@ in the following sections.
-idirafter @var{dir}
-include @var{file} -imacros @var{file}
-iprefix @var{file} -iwithprefix @var{dir}
-iwithprefixbefore @var{dir} -isystem @var{dir}
-iwithprefixbefore @var{dir} -isystem @var{dir} -isystem-c++ @var{dir}
-M -MD -MM -MMD -MG -nostdinc -P -trigraphs
-undef -U@var{macro} -Wp,@var{option}
@end smallexample
......@@ -259,6 +259,8 @@ in the following sections.
-mcpu= -march= -mfpe=
-mstructure-size-boundary=
-mbsd -mxopen -mno-symrename
-mabort-on-noreturn
-mno-sched-prolog
@emph{Thumb Options}
-mtpcs-frame -mno-tpcs-frame
......@@ -1155,6 +1157,11 @@ offsets for adjusting the @samp{this} pointer at the call site. Newer
implementations store a single pointer to a @samp{thunk} function which
does any necessary adjustment and then calls the target function.
This option also enables a heuristic for controlling emission of
vtables; if a class has any non-inline virtual functions, the vtable
will be emitted in the translation unit containing the first one of
those.
Like all options that change the ABI, all C++ code, @emph{including
libgcc.a} must be built with the same setting of this option.
......@@ -3796,13 +3803,17 @@ suppresses this pass. The post-processor is never run when the
compiler is built for cross-compilation.
@item -mcpu=<name>
@item -mtune=<name>
@kindex -mcpu=
@kindex -mtune=
This specifies the name of the target ARM processor. GCC uses this name
to determine what kind of instructions it can use when generating
assembly code. Permissable names are: arm2, arm250, arm3, arm6, arm60,
arm600, arm610, arm620, arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi,
arm70, arm700, arm700i, arm710, arm710c, arm7100, arm7500, arm7500fe,
arm7tdmi, arm8, strongarm, strongarm110
arm7tdmi, arm8, strongarm, strongarm110, strongarm1100, arm8, arm810,
arm9, arm9tdmi. @samp{-mtune=} is a synonym for @samp{-mcpue=} to
support older versions of GCC.
@item -march=<name>
@kindex -march=
......@@ -3813,9 +3824,12 @@ of the @samp{-mcpu=} option. Permissable names are: armv2, armv2a,
armv3, armv3m, armv4, armv4t
@item -mfpe=<number>
@item -mfp=<number>
@kindex -mfpe=
@kindex -mfp=
This specifes the version of the floating point emulation available on
the target. Permissable values are 2 and 3.
the target. Permissable values are 2 and 3. @samp{-mfp=} is a synonym
for @samp{-mfpe=} to support older versions of GCC.
@item -mstructure-size-boundary=<n>
@kindex -mstructure-size-boundary
......@@ -3830,6 +3844,12 @@ libraries compiled with the other value, if they exchange information
using structures or unions. Programmers are encouraged to use the 32
value as future versions of the toolchain may default to this value.
@item -mabort-on-noreturn
@kindex -mabort-on-noreturn
@kindex -mnoabort-on-noreturn
Generate a call to the function abort at the end of a noreturn function.
It will be executed if the function tries to return.
@end table
@node Thumb Options
......@@ -4666,7 +4686,9 @@ All modules should be compiled with the same @samp{-G @var{num}} value.
@itemx -mno-regnames
On System V.4 and embedded PowerPC systems do (do not) emit register
names in the assembly language output using symbolic forms.
@end table
@node RT Options
@subsection IBM RT Options
@cindex RT options
......
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