Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
f51de793
Commit
f51de793
authored
May 08, 2008
by
Sa Liu
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
fixed subti3 pattern
From-SVN: r135073
parent
1b674de0
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
13 additions
and
7 deletions
+13
-7
gcc/config/spu/spu.md
+13
-7
No files found.
gcc/config/spu/spu.md
View file @
f51de793
...
...
@@ -1047,19 +1047,25 @@
(match_operand:TI 2 "spu_reg_operand" "r")))
(clobber (match_scratch:TI 3 "=&r"))
(clobber (match_scratch:TI 4 "=&r"))
(clobber (match_scratch:TI 5 "=&r"))]
(clobber (match_scratch:TI 5 "=&r"))
(clobber (match_scratch:TI 6 "=&r"))]
""
"bg
\t
%3,%1,%2
\n\\
"il
\t
%6,1
\n\\
bg
\t
%3,%2,%1
\n\\
xor
\t
%3,%3,%6
\n\\
sf
\t
%4,%2,%1
\n\\
shlqbyi
\t
%5,%3,4
\n\\
bg
\t
%3,%4,%5
\n\\
bg
\t
%3,%5,%4
\n\\
xor
\t
%3,%3,%6
\n\\
sf
\t
%4,%5,%4
\n\\
shlqbyi
\t
%5,%3,4
\n\\
bg
\t
%3,%4,%5
\n\\
shlqbyi
\t
%0,%3,4
\n\\
sfx
\t
%0,%5,%4"
bg
\t
%3,%5,%4
\n\\
xor
\t
%3,%3,%6
\n\\
sf
\t
%4,%5,%4
\n\\
shlqbyi
\t
%5,%3,4
\n\\
sf
\t
%0,%5,%4"
[
(set_attr "type" "multi0")
(set_attr "length" "
3
6")])
(set_attr "length" "
5
6")])
(define_insn "sub
<mode>
3"
[
(set (match_operand:VSF 0 "spu_reg_operand" "=r")
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment