Commit f4f41b4e by Ulrich Weigand Committed by Ulrich Weigand

s390.md ("*cmpdi_cct", [...]): Use %h instead of %c to print immediate operand.

	* config/s390/s390.md ("*cmpdi_cct", "*cmpsi_cct", "*cmpdi_ccs",
	"*cmpsi_ccs"): Use %h instead of %c to print immediate operand.
	("*zero_extendhisi2_64", "*zero_extendhisi2_31"): Choose based on
	TARGET_ZARCH instead of TARGET_64BIT.

From-SVN: r94877
parent f203217e
2005-02-11 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.md ("*cmpdi_cct", "*cmpsi_cct", "*cmpdi_ccs",
"*cmpsi_ccs"): Use %h instead of %c to print immediate operand.
("*zero_extendhisi2_64", "*zero_extendhisi2_31"): Choose based on
TARGET_ZARCH instead of TARGET_64BIT.
2005-02-11 Ralf Corsepius <ralf.corsepius@rtems.org> 2005-02-11 Ralf Corsepius <ralf.corsepius@rtems.org>
* config/rs6000/t-rtems: * config/rs6000/t-rtems:
......
...@@ -514,7 +514,7 @@ ...@@ -514,7 +514,7 @@
"s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
"@ "@
cgr\t%0,%1 cgr\t%0,%1
cghi\t%0,%c1 cghi\t%0,%h1
cg\t%0,%1 cg\t%0,%1
#" #"
[(set_attr "op_type" "RRE,RI,RXY,SS")]) [(set_attr "op_type" "RRE,RI,RXY,SS")])
...@@ -526,7 +526,7 @@ ...@@ -526,7 +526,7 @@
"s390_match_ccmode (insn, CCTmode)" "s390_match_ccmode (insn, CCTmode)"
"@ "@
cr\t%0,%1 cr\t%0,%1
chi\t%0,%c1 chi\t%0,%h1
c\t%0,%1 c\t%0,%1
cy\t%0,%1 cy\t%0,%1
#" #"
...@@ -552,7 +552,7 @@ ...@@ -552,7 +552,7 @@
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"@ "@
cgr\t%0,%1 cgr\t%0,%1
cghi\t%0,%c1 cghi\t%0,%h1
cg\t%0,%1" cg\t%0,%1"
[(set_attr "op_type" "RRE,RI,RXY")]) [(set_attr "op_type" "RRE,RI,RXY")])
...@@ -573,7 +573,7 @@ ...@@ -573,7 +573,7 @@
"s390_match_ccmode(insn, CCSmode)" "s390_match_ccmode(insn, CCSmode)"
"@ "@
cr\t%0,%1 cr\t%0,%1
chi\t%0,%c1 chi\t%0,%h1
c\t%0,%1 c\t%0,%1
cy\t%0,%1" cy\t%0,%1"
[(set_attr "op_type" "RR,RI,RX,RXY")]) [(set_attr "op_type" "RR,RI,RX,RXY")])
...@@ -2776,7 +2776,7 @@ ...@@ -2776,7 +2776,7 @@
(define_insn "*zero_extendhisi2_64" (define_insn "*zero_extendhisi2_64"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT" "TARGET_ZARCH"
"llgh\t%0,%1" "llgh\t%0,%1"
[(set_attr "op_type" "RXY")]) [(set_attr "op_type" "RXY")])
...@@ -2784,7 +2784,7 @@ ...@@ -2784,7 +2784,7 @@
[(set (match_operand:SI 0 "register_operand" "=&d") [(set (match_operand:SI 0 "register_operand" "=&d")
(zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"!TARGET_64BIT" "!TARGET_ZARCH"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 0) (const_int 0)) [(set (match_dup 0) (const_int 0))
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment