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riscv-gcc-1
Commit f4af595f by Alexander Ivchenko Committed by Kirill Yukhin
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gcc/ 

        * common/config/i386/i386-common.c
	(OPTION_MASK_ISA_AVX512VL_SET): Define.
	(OPTION_MASK_ISA_AVX512F_UNSET): Update.
	(ix86_handle_option): Handle OPT_mavx512vl.
	* config/i386/cpuid.h (bit_AVX512VL): Define.
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512vl,
	set -mavx512vl accordingly.
	* config/i386/i386-c.c (ix86_target_macros_internal): Handle
	OPTION_MASK_ISA_AVX512VL.
	* config/i386/i386.c (ix86_target_string): Handle -mavx512vl.
	(ix86_option_override_internal): Define PTA_AVX512VL, handle
	PTA_AVX512VL and OPTION_MASK_ISA_AVX512VL.
	(ix86_valid_target_attribute_inner_p): Handle OPT_mavx512vl.
	* config/i386/i386.h (TARGET_AVX512VL): Define.
	(TARGET_AVX512VL_P(x)): Ditto.
	* config/i386/i386.opt: Add mavx512vl.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r213813
parent d4759fc6
Showing with 64 additions and 3 deletions
gcc/ChangeLog
2014-08-11 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_AVX512VL_SET): Define.
(OPTION_MASK_ISA_AVX512F_UNSET): Update.
(ix86_handle_option): Handle OPT_mavx512vl.
* config/i386/cpuid.h (bit_AVX512VL): Define.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect avx512vl,
set -mavx512vl accordingly.
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
OPTION_MASK_ISA_AVX512VL.
* config/i386/i386.c (ix86_target_string): Handle -mavx512vl.
(ix86_option_override_internal): Define PTA_AVX512VL, handle
PTA_AVX512VL and OPTION_MASK_ISA_AVX512VL.
(ix86_valid_target_attribute_inner_p): Handle OPT_mavx512vl.
* config/i386/i386.h (TARGET_AVX512VL): Define.
(TARGET_AVX512VL_P(x)): Ditto.
* config/i386/i386.opt: Add mavx512vl.
2014-08-11 Felix Yang <fei.yang0953@gmail.com> 2014-08-11 Felix Yang <fei.yang0953@gmail.com>
PR tree-optimization/62073 PR tree-optimization/62073
......
gcc/common/config/i386/i386-common.c
...@@ -69,6 +69,8 @@ along with GCC; see the file COPYING3. If not see ...@@ -69,6 +69,8 @@ along with GCC; see the file COPYING3. If not see
(OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET) (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512BW_SET \ #define OPTION_MASK_ISA_AVX512BW_SET \
(OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET) (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_AVX512VL_SET \
(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
...@@ -157,12 +159,14 @@ along with GCC; see the file COPYING3. If not see ...@@ -157,12 +159,14 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA_AVX512F_UNSET \ #define OPTION_MASK_ISA_AVX512F_UNSET \
(OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
| OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
| OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET) | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
| OPTION_MASK_ISA_AVX512VL_UNSET)
#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
#define OPTION_MASK_ISA_AVX512BW_UNSET OPTION_MASK_ISA_AVX512BW #define OPTION_MASK_ISA_AVX512BW_UNSET OPTION_MASK_ISA_AVX512BW
#define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
...@@ -426,6 +430,19 @@ ix86_handle_option (struct gcc_options *opts, ...@@ -426,6 +430,19 @@ ix86_handle_option (struct gcc_options *opts,
} }
return true; return true;
case OPT_mavx512vl:
if (value)
{
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
}
else
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
}
return true;
case OPT_mfma: case OPT_mfma:
if (value) if (value)
{ {
......
gcc/config/i386/cpuid.h
...@@ -82,6 +82,7 @@ ...@@ -82,6 +82,7 @@
#define bit_AVX512CD (1 << 28) #define bit_AVX512CD (1 << 28)
#define bit_SHA (1 << 29) #define bit_SHA (1 << 29)
#define bit_AVX512BW (1 << 30) #define bit_AVX512BW (1 << 30)
#define bit_AVX512VL (1 << 31)
/* %ecx */ /* %ecx */
#define bit_PREFETCHWT1 (1 << 0) #define bit_PREFETCHWT1 (1 << 0)
......
gcc/config/i386/driver-i386.c
...@@ -411,7 +411,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) ...@@ -411,7 +411,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0; unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0; unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0; unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
unsigned int has_avx512dq = 0, has_avx512bw = 0; unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
bool arch; bool arch;
...@@ -492,6 +492,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) ...@@ -492,6 +492,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
has_clflushopt = ebx & bit_CLFLUSHOPT; has_clflushopt = ebx & bit_CLFLUSHOPT;
has_avx512dq = ebx & bit_AVX512DQ; has_avx512dq = ebx & bit_AVX512DQ;
has_avx512bw = ebx & bit_AVX512BW; has_avx512bw = ebx & bit_AVX512BW;
has_avx512vl = ebx & bit_AVX512VL;
has_prefetchwt1 = ecx & bit_PREFETCHWT1; has_prefetchwt1 = ecx & bit_PREFETCHWT1;
} }
...@@ -906,6 +907,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) ...@@ -906,6 +907,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves"; const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq"; const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw"; const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3, options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
sse4a, cx16, sahf, movbe, aes, sha, pclmul, sse4a, cx16, sahf, movbe, aes, sha, pclmul,
...@@ -914,7 +916,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) ...@@ -914,7 +916,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx, hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
fxsr, xsave, xsaveopt, avx512f, avx512er, fxsr, xsave, xsaveopt, avx512f, avx512er,
avx512cd, avx512pf, prefetchwt1, clflushopt, avx512cd, avx512pf, prefetchwt1, clflushopt,
xsavec, xsaves, avx512dq, avx512bw, NULL); xsavec, xsaves, avx512dq, avx512bw, avx512vl,
NULL);
} }
done: done:
......
gcc/config/i386/i386-c.c
...@@ -349,6 +349,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, ...@@ -349,6 +349,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__AVX512DQ__"); def_or_undef (parse_in, "__AVX512DQ__");
if (isa_flag & OPTION_MASK_ISA_AVX512BW) if (isa_flag & OPTION_MASK_ISA_AVX512BW)
def_or_undef (parse_in, "__AVX512BW__"); def_or_undef (parse_in, "__AVX512BW__");
if (isa_flag & OPTION_MASK_ISA_AVX512VL)
def_or_undef (parse_in, "__AVX512VL__");
if (isa_flag & OPTION_MASK_ISA_FMA) if (isa_flag & OPTION_MASK_ISA_FMA)
def_or_undef (parse_in, "__FMA__"); def_or_undef (parse_in, "__FMA__");
if (isa_flag & OPTION_MASK_ISA_RTM) if (isa_flag & OPTION_MASK_ISA_RTM)
......
gcc/config/i386/i386.c
...@@ -2594,6 +2594,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, ...@@ -2594,6 +2594,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch,
{ "-mavx512pf", OPTION_MASK_ISA_AVX512PF }, { "-mavx512pf", OPTION_MASK_ISA_AVX512PF },
{ "-mavx512dq", OPTION_MASK_ISA_AVX512DQ }, { "-mavx512dq", OPTION_MASK_ISA_AVX512DQ },
{ "-mavx512bw", OPTION_MASK_ISA_AVX512BW }, { "-mavx512bw", OPTION_MASK_ISA_AVX512BW },
{ "-mavx512vl", OPTION_MASK_ISA_AVX512VL },
{ "-msse4a", OPTION_MASK_ISA_SSE4A }, { "-msse4a", OPTION_MASK_ISA_SSE4A },
{ "-msse4.2", OPTION_MASK_ISA_SSE4_2 }, { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
{ "-msse4.1", OPTION_MASK_ISA_SSE4_1 }, { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
...@@ -3126,6 +3127,7 @@ ix86_option_override_internal (bool main_args_p, ...@@ -3126,6 +3127,7 @@ ix86_option_override_internal (bool main_args_p,
#define PTA_XSAVES (HOST_WIDE_INT_1 << 49) #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
#define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50) #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
#define PTA_AVX512BW (HOST_WIDE_INT_1 << 51) #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
#define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
#define PTA_CORE2 \ #define PTA_CORE2 \
(PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \ (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
...@@ -3699,6 +3701,9 @@ ix86_option_override_internal (bool main_args_p, ...@@ -3699,6 +3701,9 @@ ix86_option_override_internal (bool main_args_p,
if (processor_alias_table[i].flags & PTA_AVX512BW if (processor_alias_table[i].flags & PTA_AVX512BW
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512BW)) && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512BW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW; opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW;
if (processor_alias_table[i].flags & PTA_AVX512VL
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL;
if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
x86_prefetch_sse = true; x86_prefetch_sse = true;
...@@ -4557,6 +4562,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[], ...@@ -4557,6 +4562,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[],
IX86_ATTR_ISA ("avx512cd", OPT_mavx512cd), IX86_ATTR_ISA ("avx512cd", OPT_mavx512cd),
IX86_ATTR_ISA ("avx512dq", OPT_mavx512dq), IX86_ATTR_ISA ("avx512dq", OPT_mavx512dq),
IX86_ATTR_ISA ("avx512bw", OPT_mavx512bw), IX86_ATTR_ISA ("avx512bw", OPT_mavx512bw),
IX86_ATTR_ISA ("avx512vl", OPT_mavx512vl),
IX86_ATTR_ISA ("mmx", OPT_mmmx), IX86_ATTR_ISA ("mmx", OPT_mmmx),
IX86_ATTR_ISA ("pclmul", OPT_mpclmul), IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
IX86_ATTR_ISA ("popcnt", OPT_mpopcnt), IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
gcc/config/i386/i386.h
...@@ -75,6 +75,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ...@@ -75,6 +75,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x)
#define TARGET_AVX512BW TARGET_ISA_AVX512BW #define TARGET_AVX512BW TARGET_ISA_AVX512BW
#define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x)
#define TARGET_AVX512VL TARGET_ISA_AVX512VL
#define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x)
#define TARGET_FMA TARGET_ISA_FMA #define TARGET_FMA TARGET_ISA_FMA
#define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x)
#define TARGET_SSE4A TARGET_ISA_SSE4A #define TARGET_SSE4A TARGET_ISA_SSE4A
......
gcc/config/i386/i386.opt
...@@ -649,6 +649,10 @@ mavx512bw ...@@ -649,6 +649,10 @@ mavx512bw
Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation
mavx512vl
Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation
mfma mfma
Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
......
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