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Commit f4aa3848 by Andreas Krebbel Committed by Andreas Krebbel
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2064.md: Remove trailing whitespaces. 

2009-05-18  Andreas Krebbel  <krebbel1@de.ibm.com>

	* config/s390/2064.md: Remove trailing whitespaces.
	* config/s390/2084.md: Likewise.
	* config/s390/constraints.md: Likewise.
	* config/s390/fixdfdi.h: Likewise.
	* config/s390/libgcc-glibc.ver: Likewise.
	* config/s390/s390-modes.def: Likewise.
	* config/s390/s390-protos.h: Likewise.
	* config/s390/s390.c: Likewise.
	* config/s390/s390.h: Likewise.
	* config/s390/s390.md: Likewise.
	* config/s390/tpf-unwind.h: Likewise.

From-SVN: r147660
parent bfa31dad
Showing with 166 additions and 152 deletions
gcc/ChangeLog
2009-05-18 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/2064.md: Remove trailing whitespaces.
* config/s390/2084.md: Likewise.
* config/s390/constraints.md: Likewise.
* config/s390/fixdfdi.h: Likewise.
* config/s390/libgcc-glibc.ver: Likewise.
* config/s390/s390-modes.def: Likewise.
* config/s390/s390-protos.h: Likewise.
* config/s390/s390.c: Likewise.
* config/s390/s390.h: Likewise.
* config/s390/s390.md: Likewise.
* config/s390/tpf-unwind.h: Likewise.
2009-05-18 Maxim Kuvyrkov <maxim@codesourcery.com>
* config/m68k/m68k.c (m68k_legitimize_address): Fix typo in signature.
......
gcc/config/s390/2064.md
......@@ -21,22 +21,22 @@
;;
;; References:
;; The microarchitecture of the IBM eServer z900 processor.
;; The microarchitecture of the IBM eServer z900 processor.
;; E.M. Schwarz et al.
;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
;;
;;
;; z900 (cpu 2064) pipeline
;;
;;
;; dec
;; --> | <---
;; LA bypass | agen |
;; | | |
;; | | |
;; --- c1 | Load bypass
;; | |
;; | |
;; c2----
;; |
;; e1
;; |
;; e1
;; |
;; wr
;; This scheduler description is also used for the g5 and g6.
......@@ -46,12 +46,12 @@
(define_cpu_unit "z_wr" "z_ipu")
(define_insn_reservation "z_la" 1
(define_insn_reservation "z_la" 1
(and (eq_attr "cpu" "z900,g5,g6")
(eq_attr "type" "la"))
"z_e1,z_wr")
(define_insn_reservation "z_larl" 1
(define_insn_reservation "z_larl" 1
(and (eq_attr "cpu" "z900,g5,g6")
(eq_attr "type" "larl"))
"z_e1,z_wr")
......@@ -101,32 +101,32 @@
"z_e1,z_wr")
;;
;; s390_agen_dep_p returns 1, if a register is set in the
;; s390_agen_dep_p returns 1, if a register is set in the
;; first insn and used in the dependent insn to form a address.
;;
;;
;; If an instruction uses a register to address memory, it needs
;; to be set 5 cycles in advance.
;;
;;
(define_bypass 5 "z_int,z_agen"
(define_bypass 5 "z_int,z_agen"
"z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
;;
;; A load type instruction uses a bypass to feed the result back
;; to the address generation pipeline stage.
;; A load type instruction uses a bypass to feed the result back
;; to the address generation pipeline stage.
;;
(define_bypass 3 "z_load"
(define_bypass 3 "z_load"
"z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
;;
;; A load address type instruction uses a bypass to feed the
;; result back to the address generation pipeline stage.
;; A load address type instruction uses a bypass to feed the
;; result back to the address generation pipeline stage.
;;
(define_bypass 2 "z_larl,z_la"
(define_bypass 2 "z_larl,z_la"
"z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
......
gcc/config/s390/2084.md
......@@ -76,38 +76,38 @@
(define_insn_reservation "x_lr" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "lr"))
"x-e1-st,x-wr-st")
"x-e1-st,x-wr-st")
(define_insn_reservation "x_la" 1
(define_insn_reservation "x_la" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "la"))
"x-e1-st,x-wr-st")
"x-e1-st,x-wr-st")
(define_insn_reservation "x_larl" 1
(define_insn_reservation "x_larl" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "larl"))
"x-e1-st,x-wr-st")
"x-e1-st,x-wr-st")
(define_insn_reservation "x_load" 1
(define_insn_reservation "x_load" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "load"))
"x-e1-st+x-mem,x-wr-st")
"x-e1-st+x-mem,x-wr-st")
(define_insn_reservation "x_store" 1
(define_insn_reservation "x_store" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "store"))
"x-e1-st+x_store_tok,x-wr-st")
"x-e1-st+x_store_tok,x-wr-st")
(define_insn_reservation "x_branch" 1
(define_insn_reservation "x_branch" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "branch"))
"x_e1_r,x_wr_r")
"x_e1_r,x_wr_r")
(define_insn_reservation "x_call" 5
(define_insn_reservation "x_call" 5
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "jsr"))
"x-e1-np*5,x-wr-np")
(define_insn_reservation "x_mul_hi" 2
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "imulhi"))
......@@ -123,162 +123,162 @@
(eq_attr "type" "idiv"))
"x-e1-np*10,x-wr-np")
(define_insn_reservation "x_sem" 17
(define_insn_reservation "x_sem" 17
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "sem"))
"x-e1-np+x-mem,x-e1-np*16,x-wr-st")
"x-e1-np+x-mem,x-e1-np*16,x-wr-st")
;;
;; Multicycle insns
;;
(define_insn_reservation "x_cs" 1
(define_insn_reservation "x_cs" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "cs"))
"x-e1-np,x-wr-np")
"x-e1-np,x-wr-np")
(define_insn_reservation "x_vs" 1
(define_insn_reservation "x_vs" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "vs"))
"x-e1-np*10,x-wr-np")
"x-e1-np*10,x-wr-np")
(define_insn_reservation "x_stm" 1
(define_insn_reservation "x_stm" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "stm"))
"(x-e1-np+x_store_tok)*10,x-wr-np")
"(x-e1-np+x_store_tok)*10,x-wr-np")
(define_insn_reservation "x_lm" 1
(define_insn_reservation "x_lm" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "lm"))
"x-e1-np*10,x-wr-np")
"x-e1-np*10,x-wr-np")
(define_insn_reservation "x_other" 1
(define_insn_reservation "x_other" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "other"))
"x-e1-np,x-wr-np")
"x-e1-np,x-wr-np")
;;
;; Floating point insns
;;
(define_insn_reservation "x_fsimptf" 7
(define_insn_reservation "x_fsimptf" 7
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fsimptf"))
"x_e1_t*2,x-wr-fp")
"x_e1_t*2,x-wr-fp")
(define_insn_reservation "x_fsimpdf" 6
(define_insn_reservation "x_fsimpdf" 6
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fsimpdf,fmuldf"))
"x_e1_t,x-wr-fp")
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_fsimpsf" 6
(define_insn_reservation "x_fsimpsf" 6
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fsimpsf,fmulsf"))
"x_e1_t,x-wr-fp")
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_fmultf" 33
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fmultf"))
"x_e1_t*27,x-wr-fp")
"x_e1_t*27,x-wr-fp")
(define_insn_reservation "x_fdivtf" 82
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fdivtf,fsqrttf"))
"x_e1_t*76,x-wr-fp")
"x_e1_t*76,x-wr-fp")
(define_insn_reservation "x_fdivdf" 36
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fdivdf,fsqrtdf"))
"x_e1_t*30,x-wr-fp")
"x_e1_t*30,x-wr-fp")
(define_insn_reservation "x_fdivsf" 36
(define_insn_reservation "x_fdivsf" 36
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fdivsf,fsqrtsf"))
"x_e1_t*30,x-wr-fp")
"x_e1_t*30,x-wr-fp")
(define_insn_reservation "x_floadtf" 6
(define_insn_reservation "x_floadtf" 6
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "floadtf"))
"x_e1_t,x-wr-fp")
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_floaddf" 6
(define_insn_reservation "x_floaddf" 6
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "floaddf"))
"x_e1_t,x-wr-fp")
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_floadsf" 6
(define_insn_reservation "x_floadsf" 6
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "floadsf"))
"x_e1_t,x-wr-fp")
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_fstoredf" 1
(define_insn_reservation "x_fstoredf" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fstoredf"))
"x_e1_t,x-wr-fp")
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_fstoresf" 1
(define_insn_reservation "x_fstoresf" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "fstoresf"))
"x_e1_t,x-wr-fp")
"x_e1_t,x-wr-fp")
(define_insn_reservation "x_ftrunctf" 16
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "ftrunctf"))
"x_e1_t*10,x-wr-fp")
"x_e1_t*10,x-wr-fp")
(define_insn_reservation "x_ftruncdf" 11
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "ftruncdf"))
"x_e1_t*5,x-wr-fp")
"x_e1_t*5,x-wr-fp")
(define_insn_reservation "x_ftoi" 1
(define_insn_reservation "x_ftoi" 1
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "ftoi"))
"x_e1_t*3,x-wr-fp")
"x_e1_t*3,x-wr-fp")
(define_insn_reservation "x_itof" 7
(define_insn_reservation "x_itof" 7
(and (eq_attr "cpu" "z990,z9_109")
(eq_attr "type" "itoftf,itofdf,itofsf"))
"x_e1_t*3,x-wr-fp")
"x_e1_t*3,x-wr-fp")
(define_bypass 1 "x_fsimpdf" "x_fstoredf")
(define_bypass 1 "x_fsimpsf" "x_fstoresf")
(define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf")
(define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf")
;;
;; s390_agen_dep_p returns 1, if a register is set in the
;; s390_agen_dep_p returns 1, if a register is set in the
;; first insn and used in the dependent insn to form a address.
;;
;;
;; If an instruction uses a register to address memory, it needs
;; to be set 5 cycles in advance.
;;
;;
(define_bypass 5 "x_int,x_agen,x_lr"
(define_bypass 5 "x_int,x_agen,x_lr"
"x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
"s390_agen_dep_p")
(define_bypass 9 "x_int,x_agen,x_lr"
(define_bypass 9 "x_int,x_agen,x_lr"
"x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
"s390_agen_dep_p")
;;
;; A load type instruction uses a bypass to feed the result back
;; to the address generation pipeline stage.
;; A load type instruction uses a bypass to feed the result back
;; to the address generation pipeline stage.
;;
(define_bypass 4 "x_load"
(define_bypass 4 "x_load"
"x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
"s390_agen_dep_p")
......@@ -288,11 +288,11 @@
"s390_agen_dep_p")
;;
;; A load address type instruction uses a bypass to feed the
;; result back to the address generation pipeline stage.
;; A load address type instruction uses a bypass to feed the
;; result back to the address generation pipeline stage.
;;
(define_bypass 3 "x_larl,x_la"
(define_bypass 3 "x_larl,x_la"
"x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
"s390_agen_dep_p")
......
gcc/config/s390/constraints.md
......@@ -76,27 +76,27 @@
;; Register constraints.
;;
(define_register_constraint "a"
(define_register_constraint "a"
"ADDR_REGS"
"Any address register from 1 to 15.")
(define_register_constraint "c"
(define_register_constraint "c"
"CC_REGS"
"Condition code register 33")
(define_register_constraint "d"
(define_register_constraint "d"
"GENERAL_REGS"
"Any register from 0 to 15")
(define_register_constraint "f"
(define_register_constraint "f"
"FP_REGS"
"Floating point registers")
(define_register_constraint "t"
(define_register_constraint "t"
"ACCESS_REGS"
"@internal
Access registers 36 and 37")
......@@ -187,9 +187,9 @@
;; is specified instead of a part number, the constraint matches
;; if there is any single part with non-default value.
;;
;; The following patterns define only those constraints that are actually
;; used in s390.md. If you need an additional one, simply add it in the
;; obvious way. Function s390_N_constraint_str is ready to handle all
;; The following patterns define only those constraints that are actually
;; used in s390.md. If you need an additional one, simply add it in the
;; obvious way. Function s390_N_constraint_str is ready to handle all
;; combinations.
;;
......@@ -409,53 +409,53 @@ constraint."
|| s390_mem_constraint (\"T\", op)"))
(define_memory_constraint "AQ"
"@internal
"@internal
Offsettable memory reference without index register and with short displacement"
(match_test "s390_mem_constraint (\"AQ\", op)"))
(define_memory_constraint "AR"
"@internal
"@internal
Offsettable memory reference with index register and short displacement"
(match_test "s390_mem_constraint (\"AR\", op)"))
(define_memory_constraint "AS"
"@internal
"@internal
Offsettable memory reference without index register but with long displacement"
(match_test "s390_mem_constraint (\"AS\", op)"))
(define_memory_constraint "AT"
"@internal
"@internal
Offsettable memory reference with index register and long displacement"
(match_test "s390_mem_constraint (\"AT\", op)"))
(define_constraint "BQ"
"@internal
Memory reference without index register and with short
"@internal
Memory reference without index register and with short
displacement that does *not* refer to a literal pool entry."
(match_test "s390_mem_constraint (\"BQ\", op)"))
(define_constraint "BR"
"@internal
"@internal
Memory reference with index register and short displacement that
does *not* refer to a literal pool entry. "
(match_test "s390_mem_constraint (\"BR\", op)"))
(define_constraint "BS"
"@internal
"@internal
Memory reference without index register but with long displacement
that does *not* refer to a literal pool entry. "
(match_test "s390_mem_constraint (\"BS\", op)"))
(define_constraint "BT"
"@internal
"@internal
Memory reference with index register and long displacement that
does *not* refer to a literal pool entry. "
(match_test "s390_mem_constraint (\"BT\", op)"))
......
gcc/config/s390/fixdfdi.h
......@@ -63,12 +63,12 @@ __fixunstfdi (long double a1)
if (!EXPD (dl1) || SIGND(dl1))
return 0;
/* The exponent - considered the binary point at the right end of
/* The exponent - considered the binary point at the right end of
the mantissa. */
exp = EXPD (dl1) - EXPONENT_BIAS - MANTISSA_BITS;
/* number < 1: If the mantissa would need to be right-shifted more bits than
its size (plus the implied one bit on the left) the result would be
its size (plus the implied one bit on the left) the result would be
zero. */
if (exp <= -PRECISION)
return 0;
......@@ -238,7 +238,7 @@ __fixunsdfdi (double a1)
/* shift down until exp < 12 or l = 0 */
if (exp > 0)
l <<= exp;
else
else
l >>= -exp;
return l;
......@@ -313,7 +313,7 @@ __fixdfdi (double a1)
/* shift down until exp < 12 or l = 0 */
if (exp > 0)
l <<= exp;
else
else
l >>= -exp;
return (SIGND (dl1) ? -l : l);
......@@ -381,7 +381,7 @@ __fixunssfdi (float a1)
if (exp > 0)
l <<= exp;
else
else
l >>= -exp;
return l;
......@@ -452,7 +452,7 @@ __fixsfdi (float a1)
if (exp > 0)
l <<= exp;
else
else
l >>= -exp;
return (SIGN (fl1) ? -l : l);
......
gcc/config/s390/libgcc-glibc.ver
......@@ -23,7 +23,7 @@
# to defer implementation of these routines to libgcc.so via DT_AUXILIARY.
# Note that we cannot use the default libgcc-glibc.ver file on s390x,
# because GLIBC_2.0 does not exist on this architecture, as the first
# because GLIBC_2.0 does not exist on this architecture, as the first
# ever glibc release on the platform was GLIBC_2.2.
%ifndef __s390x__
......
gcc/config/s390/s390-modes.def
......@@ -45,8 +45,8 @@ Signed compares
CCS: EQ LT GT UNORDERED (LTGFR, LTGR, LTR, ICM/Y,
LTDBR, LTDR, LTEBR, LTER,
CG/R, C/R/Y, CGHI, CHI,
CDB/R, CD/R, CEB/R, CE/R,
CG/R, C/R/Y, CGHI, CHI,
CDB/R, CD/R, CEB/R, CE/R,
ADB/R, AEB/R, SDB/R, SEB/R,
SRAG, SRA, SRDA)
CCSR: EQ GT LT UNORDERED (CGF/R, CH/Y)
......@@ -60,7 +60,7 @@ CCAN: EQ LT GT GT (AGHI, AHI)
Condition codes of unsigned adds and subs
CCL: EQ NE EQ NE (ALGF/R, ALG/R, AL/R/Y,
ALCG/R, ALC/R,
ALCG/R, ALC/R,
SLGF/R, SLG/R, SL/R/Y,
SLBG/R, SLB/R)
CCL1: GEU GEU LTU LTU (ALG/R, AL/R/Y)
......@@ -69,14 +69,14 @@ CCL3: EQ LTU EQ GTU (SLG/R, SL/R/Y)
Test under mask checks
CCT: EQ NE NE NE (ICM/Y, TML, CG/R, CGHI,
CCT: EQ NE NE NE (ICM/Y, TML, CG/R, CGHI,
C/R/Y, CHI, NG/R, N/R/Y,
OG/R, O/R/Y, XG/R, X/R/Y)
CCT1: NE EQ NE NE (TMH, TML)
CCT2: NE NE EQ NE (TMH, TML)
CCT3: NE NE NE EQ (TMH, TML)
CCA and CCT modes are request only modes. These modes are never returned by
CCA and CCT modes are request only modes. These modes are never returned by
s390_select_cc_mode. They are only intended to match other modes.
Requested mode -> Destination CC register mode
......@@ -89,11 +89,11 @@ CCA -> CCAP, CCAN
CCAP, CCAN
The CC obtained from add instruction usually can't be used for comparisons
The CC obtained from add instruction usually can't be used for comparisons
because its coupling with overflow flag. In case of an overflow the
less than/greater than data are lost. Nevertheless a comparison can be done
whenever immediate values are involved because they are known at compile time.
If you know whether the used constant is positive or negative you can predict
If you know whether the used constant is positive or negative you can predict
the sign of the result even in case of an overflow.
......@@ -103,7 +103,7 @@ If bits of an integer masked with an AND instruction are checked, the test under
mask instructions turn out to be very handy for a set of special cases.
The simple cases are checks whether all masked bits are zero or ones:
int a;
int a;
if ((a & (16 + 128)) == 0) -> CCT/CCZ
if ((a & (16 + 128)) == 16 + 128) -> CCT3
......@@ -120,15 +120,15 @@ CCSR, CCUR
There are several instructions comparing 32 bit with 64-bit unsigned/signed
values. Such instructions can be considered to have a builtin zero/sign_extend.
The problem is that in the RTL (to be canonical) the zero/sign extended operand
has to be the first one but the machine instructions like it the other way
around. The following both modes can be considered as CCS and CCU modes with
The problem is that in the RTL (to be canonical) the zero/sign extended operand
has to be the first one but the machine instructions like it the other way
around. The following both modes can be considered as CCS and CCU modes with
exchanged operands.
CCL1, CCL2
These modes represent the result of overflow checks.
These modes represent the result of overflow checks.
if (a + b < a) -> CCL1 state of the carry bit (CC2 | CC3)
if (a - b > a) -> CCL2 state of the borrow bit (CC0 | CC1)
......@@ -142,7 +142,7 @@ CCL3
A logical subtract instruction sets the borrow bit in case of an overflow.
The resulting condition code of those instructions is represented by the
CCL3 mode. Together with the CCU mode this mode is used for jumpless
CCL3 mode. Together with the CCU mode this mode is used for jumpless
implementations of several if-constructs - see s390_expand_addcc for more
details.
......@@ -152,7 +152,7 @@ The compare and swap instructions sets the condition code to 0/1 if the
operands were equal/unequal. The CCZ1 mode ensures the result can be
effectively placed into a register.
*/
*/
CC_MODE (CCZ);
......
gcc/config/s390/s390-protos.h
......@@ -22,7 +22,7 @@ along with GCC; see the file COPYING3. If not see
/* Prototypes of functions used for constraint evaluation in
/* Prototypes of functions used for constraint evaluation in
constraints.c. */
extern int s390_mem_constraint (const char *str, rtx op);
......@@ -92,7 +92,7 @@ extern void s390_expand_cmpmem (rtx, rtx, rtx, rtx);
extern bool s390_expand_addcc (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
extern bool s390_expand_insv (rtx, rtx, rtx, rtx);
extern void s390_expand_cs_hqi (enum machine_mode, rtx, rtx, rtx, rtx);
extern void s390_expand_atomic (enum machine_mode, enum rtx_code,
extern void s390_expand_atomic (enum machine_mode, enum rtx_code,
rtx, rtx, rtx, bool);
extern rtx s390_return_addr_rtx (int, rtx);
extern rtx s390_back_chain_rtx (void);
......
gcc/config/s390/s390.h
......@@ -180,7 +180,7 @@ extern int s390_arch_flags;
#define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7)
#define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6)
/* For signbit, the BFP-DFP-difference makes no difference. */
/* For signbit, the BFP-DFP-difference makes no difference. */
#define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \
| S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \
| S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\
......@@ -298,10 +298,10 @@ if (INTEGRAL_MODE_P (MODE) && \
correspond to actual hardware:
Reg 32: Argument pointer
Reg 33: Condition code
Reg 34: Frame pointer
Reg 34: Frame pointer
Reg 35: Return address pointer
Registers 36 and 37 are mapped to access registers
Registers 36 and 37 are mapped to access registers
0 and 1, used to implement thread-local storage. */
#define FIRST_PSEUDO_REGISTER 38
......@@ -455,7 +455,7 @@ if (INTEGRAL_MODE_P (MODE) && \
enum reg_class
{
NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS,
ADDR_CC_REGS, GENERAL_CC_REGS,
ADDR_CC_REGS, GENERAL_CC_REGS,
FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
ALL_REGS, LIM_REG_CLASSES
};
......@@ -575,7 +575,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
the argument area. */
#define FIRST_PARM_OFFSET(FNDECL) 0
/* Defining this macro makes __builtin_frame_address(0) and
/* Defining this macro makes __builtin_frame_address(0) and
__builtin_return_address(0) work with -fomit-frame-pointer. */
#define INITIAL_FRAME_ADDRESS_RTX \
(plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
......@@ -615,7 +615,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
/* Describe how we implement __builtin_eh_return. */
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
#define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx)
/* Select a format to encode pointers in exception handling data. */
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
(flag_pic \
......@@ -807,7 +807,7 @@ do { \
#define SLOW_BYTE_ACCESS 1
/* An integer expression for the size in bits of the largest integer machine
mode that should actually be used. We allow pairs of registers. */
mode that should actually be used. We allow pairs of registers. */
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
/* The maximum number of bytes that a single instruction can move quickly
......
gcc/config/s390/s390.md
......@@ -37,7 +37,7 @@
;; %N: print the second word of a DImode operand.
;; %M: print the second word of a TImode operand.
;; %Y: print shift count operand.
;;
;;
;; %b: print integer X as if it's an unsigned byte.
;; %c: print integer X as if it's an signed byte.
;; %x: print integer X as if it's an unsigned halfword.
......@@ -154,7 +154,7 @@
(RETURN_REGNUM 14)
; Condition code register.
(CC_REGNUM 33)
; Thread local storage pointer register.
; Thread local storage pointer register.
(TP_REGNUM 36)
])
......@@ -220,7 +220,7 @@
;; reg: Instruction does not use the agen unit
(define_attr "atype" "agen,reg"
(if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
(if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
(const_string "reg")
(const_string "agen")))
......@@ -319,7 +319,7 @@
;; These mode iterators allow floating point patterns to be generated from the
;; same template.
(define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
(define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
(SD "TARGET_HARD_DFP")])
(define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
(define_mode_iterator FPALL [TF DF SF TD DD SD])
......@@ -360,15 +360,15 @@
;; This iterator and attribute allow to combine most atomic operations.
(define_code_iterator ATOMIC [and ior xor plus minus mult])
(define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
(define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
(plus "add") (minus "sub") (mult "nand")])
;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
(define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
;; SDmode.
(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
......@@ -382,14 +382,14 @@
;; dfp variants in a single insn definition.
;; This attribute is used to set op_type accordingly.
(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
(DD "RRR") (SD "RRR")])
;; This attribute is used in the operand constraint list in order to have the
;; This attribute is used in the operand constraint list in order to have the
;; first and the second operand match for bfp modes.
(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
;; This attribute is used in the operand list of the instruction to have an
;; This attribute is used in the operand list of the instruction to have an
;; additional operand for the dfp instructions.
(define_mode_attr op1 [(TF "") (DF "") (SF "")
(TD "%1,") (DD "%1,") (SD "%1,")])
......
gcc/config/s390/tpf-unwind.h
......@@ -46,7 +46,7 @@ __isPATrange (void *addr)
/* TPF return address offset from start of stack frame. */
#define TPFRA_OFFSET 168
/* Exceptions macro defined for TPF so that functions without
/* Exceptions macro defined for TPF so that functions without
dwarf frame information can be used with exceptions. */
#define MD_FALLBACK_FRAME_STATE_FOR s390_fallback_frame_state
......@@ -165,20 +165,20 @@ __tpf_eh_return (void *target)
/* Begin looping through stack frames. Stop if invalid
code information is retrieved or if a match between the
current stack frame iteration shared object's address
current stack frame iteration shared object's address
matches that of the target, calculated above. */
do
{
/* Get return address based on our stackptr iterator. */
current = (void *) *((unsigned long int *)
current = (void *) *((unsigned long int *)
(stackptr+RA_OFFSET));
/* Is it a Pat Stub? */
if (__isPATrange (current))
if (__isPATrange (current))
{
/* Yes it was, get real return address
/* Yes it was, get real return address
in TPF stack area. */
current = (void *) *((unsigned long int *)
current = (void *) *((unsigned long int *)
(stackptr+TPFRA_OFFSET));
is_a_stub = 1;
}
......@@ -198,7 +198,7 @@ __tpf_eh_return (void *target)
/* Yes! They are in the same module.
Force copy of TPF private stack area to
destination stack frame TPF private area. */
destination_frame = (void *) *((unsigned long int *)
destination_frame = (void *) *((unsigned long int *)
(*PREVIOUS_STACK_PTR() + R15_OFFSET));
/* Copy TPF linkage area from current frame to
......@@ -209,24 +209,24 @@ __tpf_eh_return (void *target)
/* Now overlay the
real target address into the TPF stack area of
the target frame we are jumping to. */
*((unsigned long int *) (destination_frame +
*((unsigned long int *) (destination_frame +
TPFRA_OFFSET)) = (unsigned long int) target;
/* Before returning the desired pat stub address to
the exception handling unwinder so that it can
actually do the "leap" shift out the low order
the exception handling unwinder so that it can
actually do the "leap" shift out the low order
bit designated to determine if we are in 64BIT mode.
This is necessary for CTOA stubs.
Otherwise we leap one byte past where we want to
Otherwise we leap one byte past where we want to
go to in the TPF pat stub linkage code. */
shifter = *((unsigned long int *)
shifter = *((unsigned long int *)
(stackptr + RA_OFFSET));
shifter &= ~1ul;
/* Store Pat Stub Address in destination Stack Frame. */
*((unsigned long int *) (destination_frame +
RA_OFFSET)) = shifter;
RA_OFFSET)) = shifter;
/* Re-adjust pat stub address to go to correct place
in linkage. */
......
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