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Commit f466596d by Oleg Endo
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re PR target/88630 (Incorrect float negating together with convertion to int on ST-40) 

gcc/
	PR target/88630
	* config/sh/sh.h (TARGET_FPU_SH4_300): New macro.
	* config/sh/sh.c (sh_option_override): Enable fsca and fsrra insns
	also for TARGET_FPU_SH4_300.
	(sh_emit_mode_set): Check for TARGET_FPU_SH4_300 instead of
	TARGET_SH4_300.
	* config/sh/sh.md (toggle_pr): Add TARGET_FPU_SH4_300 condition.
	(negsf2): Expand to either negsf2_fpscr or negsf2_no_fpscr.
	(*negsf2_i): Split into ...
	(negsf2_fpscr, negsf2_no_fpscr): ... these new patterns.
	(abssf2): Expand to either abssf2_fpsc or abssf2_no_fpsc.
	(**abssf2_i): Split into ...
	(abssf2_fpscr, abssf2_no_fpscr): ... these new patterns.
	(negdf2): Expand to either negdf2_fpscr or negdf2_no_fpscr.
	(*negdf2_i): Split into ...
	(negdf2_fpscr, negdf2_no_fpscr): ... these new patterns.
	(absdf2): Expand to either absdf2_fpscr or absdf2_no_fpsc.
	(**abssf2_i): Split into ...
	(absdf2_fpscr, absdf2_no_fpscr): ... these new patterns.

From-SVN: r276809
parent 73dc68b9
Showing with 106 additions and 16 deletions
gcc/ChangeLog
2019-10-10 Oleg Endo <olegendo@gcc.gnu.org>
PR target/88630
* config/sh/sh.h (TARGET_FPU_SH4_300): New macro.
* config/sh/sh.c (sh_option_override): Enable fsca and fsrra insns
also for TARGET_FPU_SH4_300.
(sh_emit_mode_set): Check for TARGET_FPU_SH4_300 instead of
TARGET_SH4_300.
* config/sh/sh.md (toggle_pr): Add TARGET_FPU_SH4_300 condition.
(negsf2): Expand to either negsf2_fpscr or negsf2_no_fpscr.
(*negsf2_i): Split into ...
(negsf2_fpscr, negsf2_no_fpscr): ... these new patterns.
(abssf2): Expand to either abssf2_fpsc or abssf2_no_fpsc.
(**abssf2_i): Split into ...
(abssf2_fpscr, abssf2_no_fpscr): ... these new patterns.
(negdf2): Expand to either negdf2_fpscr or negdf2_no_fpscr.
(*negdf2_i): Split into ...
(negdf2_fpscr, negdf2_no_fpscr): ... these new patterns.
(absdf2): Expand to either absdf2_fpscr or absdf2_no_fpsc.
(**abssf2_i): Split into ...
(absdf2_fpscr, absdf2_no_fpscr): ... these new patterns.
2019-10-10 Richard Biener <rguenther@suse.de>
PR middle-end/92046
......
gcc/config/sh/sh.c
......@@ -958,11 +958,13 @@ sh_option_override (void)
if (flag_unsafe_math_optimizations)
{
/* Enable fsca insn for SH4A if not otherwise specified by the user. */
if (global_options_set.x_TARGET_FSCA == 0 && TARGET_SH4A_FP)
if (global_options_set.x_TARGET_FSCA == 0
&& (TARGET_SH4A_FP || TARGET_FPU_SH4_300))
TARGET_FSCA = 1;
/* Enable fsrra insn for SH4A if not otherwise specified by the user. */
if (global_options_set.x_TARGET_FSRRA == 0 && TARGET_SH4A_FP)
if (global_options_set.x_TARGET_FSRRA == 0
&& (TARGET_SH4A_FP || TARGET_FPU_SH4_300))
TARGET_FSRRA = 1;
}
......@@ -12490,7 +12492,7 @@ static void
sh_emit_mode_set (int entity ATTRIBUTE_UNUSED, int mode,
int prev_mode, HARD_REG_SET regs_live ATTRIBUTE_UNUSED)
{
if ((TARGET_SH4A_FP || TARGET_SH4_300)
if ((TARGET_SH4A_FP || TARGET_FPU_SH4_300)
&& prev_mode != FP_MODE_NONE && prev_mode != mode)
{
emit_insn (gen_toggle_pr ());
......
gcc/config/sh/sh.h
......@@ -69,6 +69,8 @@ extern int code_for_indirect_jump_scratch;
FPU is disabled (which makes it compatible with SH4al-dsp). */
#define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY)
/* True if the FPU is a SH4-300 variant. */
#define TARGET_FPU_SH4_300 (TARGET_FPU_ANY && TARGET_SH4_300)
/* This is not used by the SH2E calling convention */
#define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
......
gcc/config/sh/sh.md
......@@ -9163,7 +9163,7 @@
(xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR)))
(set (reg:SI FPSCR_MODES_REG)
(unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
"TARGET_SH4A_FP"
"TARGET_SH4A_FP || TARGET_FPU_SH4_300"
"fpchg"
[(set_attr "type" "fpscr_toggle")])
......@@ -9391,15 +9391,31 @@
(define_expand "negsf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
"TARGET_SH2E")
"TARGET_FPU_ANY"
{
if (TARGET_FPU_SH4_300)
emit_insn (gen_negsf2_fpscr (operands[0], operands[1]));
else
emit_insn (gen_negsf2_no_fpscr (operands[0], operands[1]));
DONE;
})
(define_insn "*negsf2_i"
(define_insn "negsf2_no_fpscr"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
"TARGET_SH2E"
"TARGET_FPU_ANY && !TARGET_FPU_SH4_300"
"fneg %0"
[(set_attr "type" "fmove")])
(define_insn "negsf2_fpscr"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (reg:SI FPSCR_MODES_REG))]
"TARGET_FPU_SH4_300"
"fneg %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "single")])
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
......@@ -9489,15 +9505,31 @@
(define_expand "abssf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
"TARGET_SH2E")
"TARGET_FPU_ANY"
{
if (TARGET_FPU_SH4_300)
emit_insn (gen_abssf2_fpscr (operands[0], operands[1]));
else
emit_insn (gen_abssf2_no_fpscr (operands[0], operands[1]));
DONE;
})
(define_insn "*abssf2_i"
(define_insn "abssf2_no_fpscr"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
"TARGET_SH2E"
"TARGET_FPU_ANY && !TARGET_FPU_SH4_300"
"fabs %0"
[(set_attr "type" "fmove")])
(define_insn "abssf2_fpscr"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (reg:SI FPSCR_MODES_REG))]
"TARGET_FPU_SH4_300"
"fabs %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "single")])
(define_expand "adddf3"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "")
(plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
......@@ -9673,12 +9705,28 @@
(define_expand "negdf2"
[(set (match_operand:DF 0 "fp_arith_reg_operand")
(neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
"TARGET_FPU_DOUBLE")
"TARGET_FPU_DOUBLE"
{
if (TARGET_FPU_SH4_300)
emit_insn (gen_negdf2_fpscr (operands[0], operands[1]));
else
emit_insn (gen_negdf2_no_fpscr (operands[0], operands[1]));
DONE;
})
(define_insn "*negdf2_i"
(define_insn "negdf2_fpscr"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
(use (reg:SI FPSCR_MODES_REG))]
"TARGET_FPU_SH4_300"
"fneg %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "double")])
(define_insn "negdf2_no_fpscr"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
"TARGET_FPU_DOUBLE"
"TARGET_FPU_DOUBLE && !TARGET_FPU_SH4_300"
"fneg %0"
[(set_attr "type" "fmove")])
......@@ -9704,15 +9752,31 @@
(define_expand "absdf2"
[(set (match_operand:DF 0 "fp_arith_reg_operand")
(abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
"TARGET_FPU_DOUBLE")
"TARGET_FPU_DOUBLE"
{
if (TARGET_FPU_SH4_300)
emit_insn (gen_absdf2_fpscr (operands[0], operands[1]));
else
emit_insn (gen_absdf2_no_fpscr (operands[0], operands[1]));
DONE;
})
(define_insn "*absdf2_i"
(define_insn "absdf2_no_fpscr"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
"TARGET_FPU_DOUBLE"
"TARGET_FPU_DOUBLE && !TARGET_FPU_SH4_300"
"fabs %0"
[(set_attr "type" "fmove")])
(define_insn "absdf2_fpscr"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
(use (reg:SI FPSCR_MODES_REG))]
"TARGET_FPU_SH4_300"
"fabs %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "double")])
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "fp_arith_reg_operand" "")
(float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
......
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