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Commit f337b930 by Adrian Straetling Committed by Ulrich Weigand
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s390.md: ("SHIFT"): New mode macro. 

2005-05-09  Adrian Straetling  <straetling@de.ibm.com>

	* config/s390/s390.md: ("SHIFT"): New mode macro.
	("lr", "shift"): New mode attributes.
	("ashldi3", "lshrdi3"): Merge.
	("*ashldi3_31", "*lshrdi3"_31): Merge.
	("*ashldi3_64", "*lshrdi3"_64): Merge.
	("ashlsi3", "lshrsi3"): Merge.

From-SVN: r99455
parent 9a91a21f
Showing with 39 additions and 65 deletions
gcc/ChangeLog
2005-05-09 Adrian Straetling <straetling@de.ibm.com> 2005-05-09 Adrian Straetling <straetling@de.ibm.com>
* config/s390/s390.md: ("SHIFT"): New mode macro.
("lr", "shift"): New mode attributes.
("ashldi3", "lshrdi3"): Merge.
("*ashldi3_31", "*lshrdi3"_31): Merge.
("*ashldi3_64", "*lshrdi3"_64): Merge.
("ashlsi3", "lshrsi3"): Merge.
2005-05-09 Adrian Straetling <straetling@de.ibm.com>
* config/s390/s390.md: ("DSI", "SCOND"): New mode * config/s390/s390.md: ("DSI", "SCOND"): New mode
macros. macros.
("E", "g"): New mode attributes. ("E", "g"): New mode attributes.
......
gcc/config/s390/s390.md
...@@ -259,6 +259,18 @@ ...@@ -259,6 +259,18 @@
;; This macro allows to unify all 'sCOND' patterns. ;; This macro allows to unify all 'sCOND' patterns.
(define_code_macro SCOND [ltu gtu leu geu]) (define_code_macro SCOND [ltu gtu leu geu])
;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
;; the same template.
(define_code_macro SHIFT [ashift lshiftrt])
;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
;; 'ashift' and "srdl" in 'lshiftrt'.
(define_code_attr lr [(ashift "l") (lshiftrt "r")])
;; In SHIFT templates, this attribute holds the correct standard name for the
;; pattern itself and the corresponding function calls.
(define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
;; This attribute handles differences in the instruction 'type' and will result ;; This attribute handles differences in the instruction 'type' and will result
;; in "RRE" for DImode and "RR" for SImode. ;; in "RRE" for DImode and "RR" for SImode.
...@@ -6329,35 +6341,35 @@ ...@@ -6329,35 +6341,35 @@
;; ;;
;;- Arithmetic shift instructions. ;;- Shift instructions.
;; ;;
; ;
; ashldi3 instruction pattern(s). ; (ashl|lshr)di3 instruction pattern(s).
; ;
(define_expand "ashldi3" (define_expand "<shift>di3"
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "") (SHIFT:DI (match_operand:DI 1 "register_operand" "")
(match_operand:SI 2 "shift_count_operand" "")))] (match_operand:SI 2 "shift_count_operand" "")))]
"" ""
"") "")
(define_insn "*ashldi3_31" (define_insn "*<shift>di3_31"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(ashift:DI (match_operand:DI 1 "register_operand" "0") (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y")))] (match_operand:SI 2 "shift_count_operand" "Y")))]
"!TARGET_64BIT" "!TARGET_64BIT"
"sldl\t%0,%Y2" "s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
(define_insn "*ashldi3_64" (define_insn "*<shift>di3_64"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(ashift:DI (match_operand:DI 1 "register_operand" "d") (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "shift_count_operand" "Y")))] (match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_64BIT" "TARGET_64BIT"
"sllg\t%0,%1,%Y2" "s<lr>lg\t%0,%1,%Y2"
[(set_attr "op_type" "RSE") [(set_attr "op_type" "RSE")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -6442,15 +6454,15 @@ ...@@ -6442,15 +6454,15 @@
; ;
; ashlsi3 instruction pattern(s). ; (ashl|lshr)si3 instruction pattern(s).
; ;
(define_insn "ashlsi3" (define_insn "<shift>si3"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
(ashift:SI (match_operand:SI 1 "register_operand" "0") (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y")))] (match_operand:SI 2 "shift_count_operand" "Y")))]
"" ""
"sll\t%0,%Y2" "s<lr>l\t%0,%Y2"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -6494,53 +6506,6 @@ ...@@ -6494,53 +6506,6 @@
;; ;;
;;- logical shift instructions.
;;
;
; lshrdi3 instruction pattern(s).
;
(define_expand "lshrdi3"
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
(match_operand:SI 2 "shift_count_operand" "")))]
""
"")
(define_insn "*lshrdi3_31"
[(set (match_operand:DI 0 "register_operand" "=d")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y")))]
"!TARGET_64BIT"
"srdl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(define_insn "*lshrdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "shift_count_operand" "Y")))]
"TARGET_64BIT"
"srlg\t%0,%1,%Y2"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
;
; lshrsi3 instruction pattern(s).
;
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_operand" "Y")))]
""
"srl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
;;
;; Branch instruction patterns. ;; Branch instruction patterns.
;; ;;
......
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