config.gcc (mipsisa64*-*-linux*): New configuration.

	* config.gcc (mipsisa64*-*-linux*): New configuration.  Set ISA
	to MIPS64r2 for mipsisa64r2*.
	* config/mips/mips.h (GENERATE_MIPS16E): Update comment.
	(ISA_MIPS64R2): New macro.
	(TARGET_CPU_CPP_BUILTINS, MULTILIB_ISA_DEFAULT): Handle it.
	(ISA_HAS_64BIT_REGS, ISA_HAS_MUL3, ISA_HAS_FP_CONDMOVE,
	ISA_HAS_8CC, ISA_HAS_FP4, ISA_HAS_PAIRED_SINGLE,
	ISA_HAS_MADD_MSUB, ISA_HAS_NMADD4_NMSUB4, ISA_HAS_CLZ_CLO,
	ISA_HAS_ROR, ISA_HAS_PREFETCH, ISA_HAS_PREFETCHX, ISA_HAS_SEB_SEH,
	ISA_HAS_EXT_INS, ISA_HAS_MXHC1, ISA_HAS_HILO_INTERLOCKS,
	ISA_HAS_SYNCI, MIN_FPRS_PER_FMT): Return true for ISA_MIPS64R2.
	(MIPS_ISA_LEVEL_SPEC, ASM_SPEC, LINK_SPEC): Handle -mips64r2.
	(TARGET_LOONGSON_2E, TARGET_LOONGSON_2F, TARGET_LOONGSON_2EF):
	Move up to keep list alphabetically sorted.
	(TUNE_20KC, TUNE_24K, TUNE_74K, TUNE_LOONGSON_2EF): Likewise.
	* config/mips/mips.c (mips_cpu_info_table): Add default MIPS64r2
	processor.
	* doc/invoke.texi (MIPS Options): Add -mips64r2.
	(-march=@var{arch}): Add mips64r2.

testsuite/

	* gcc.target/mips/ext-1.c: New test.

From-SVN: r138448

gcc/ChangeLog

+2008-07-31  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* config.gcc (mipsisa64r2*-*-linux*): New configuration.  Set ISA
+	to MIPS64r2.
+	* config/mips/mips.h (GENERATE_MIPS16E): Update comment.
+	(ISA_MIPS64R2): New macro.
+	(TARGET_CPU_CPP_BUILTINS, MULTILIB_ISA_DEFAULT): Handle it.
+	(ISA_HAS_64BIT_REGS, ISA_HAS_MUL3, ISA_HAS_FP_CONDMOVE,
+	ISA_HAS_8CC, ISA_HAS_FP4, ISA_HAS_PAIRED_SINGLE,
+	ISA_HAS_MADD_MSUB, ISA_HAS_NMADD4_NMSUB4, ISA_HAS_CLZ_CLO,
+	ISA_HAS_ROR, ISA_HAS_PREFETCH, ISA_HAS_PREFETCHX, ISA_HAS_SEB_SEH,
+	ISA_HAS_EXT_INS, ISA_HAS_MXHC1, ISA_HAS_HILO_INTERLOCKS,
+	ISA_HAS_SYNCI, MIN_FPRS_PER_FMT): Return true for ISA_MIPS64R2.
+	(MIPS_ISA_LEVEL_SPEC, ASM_SPEC, LINK_SPEC): Handle -mips64r2.
+	(TARGET_LOONGSON_2E, TARGET_LOONGSON_2F, TARGET_LOONGSON_2EF):
+	Move up to keep list alphabetically sorted.
+	(TUNE_20KC, TUNE_24K, TUNE_74K, TUNE_LOONGSON_2EF): Likewise.
+	* config/mips/mips.c (mips_cpu_info_table): Add default MIPS64r2
+	processor.
+	* doc/invoke.texi (MIPS Options): Add -mips64r2.
+	(-march=@var{arch}): Add mips64r2.
+
 2008-07-31  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* config/i386/darwin.h (MAIN_STACK_BOUNDARY): Define to 128.

gcc/config.gcc

@@ -1542,7 +1542,7 @@ mips*-*-netbsd*)			# NetBSD/mips, either endian.
 	target_cpu_default="MASK_ABICALLS"
 	tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h"
 	;;
-mips64*-*-linux*)
+mips64*-*-linux* | mipsisa64*-*-linux*)
 	tm_file="dbxelf.h elfos.h svr4.h linux.h ${tm_file} mips/linux.h mips/linux64.h"
 	tmake_file="${tmake_file} mips/t-linux64"
 	tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_N32"
@@ -1551,6 +1551,9 @@ mips64*-*-linux*)
 			tm_file="${tm_file} mips/st.h"
 			tmake_file="${tmake_file} mips/t-st"
 			;;
+		mipsisa64r2*-*-linux*)
+			tm_defines="${tm_defines} MIPS_ISA_DEFAULT=65"
+			;;
 	esac
 	gnu_ld=yes
 	gas=yes

gcc/config/mips/mips.c

@@ -565,6 +565,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] = {
   { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
   { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
   { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
+  /* ??? For now just tune the generic MIPS64r2 for 5KC as well.   */
+  { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
 
   /* MIPS I processors.  */
   { "r3000", PROCESSOR_R3000, 1, 0 },

gcc/doc/invoke.texi

@@ -629,7 +629,8 @@ Objective-C and Objective-C++ Dialects}.
 
 @emph{MIPS Options}
 @gccoptlist{-EL  -EB  -march=@var{arch}  -mtune=@var{arch} @gol
--mips1  -mips2  -mips3  -mips4  -mips32  -mips32r2  -mips64 @gol
+-mips1  -mips2  -mips3  -mips4  -mips32  -mips32r2 @gol
+-mips64  -mips64r2 @gol
 -mips16  -mno-mips16  -mflip-mips16 @gol
 -minterlink-mips16  -mno-interlink-mips16 @gol
 -mabi=@var{abi}  -mabicalls  -mno-abicalls @gol
@@ -11963,7 +11964,7 @@ Generate code that will run on @var{arch}, which can be the name of a
 generic MIPS ISA, or the name of a particular processor.
 The ISA names are:
 @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
-@samp{mips32}, @samp{mips32r2}, and @samp{mips64}.
+@samp{mips32}, @samp{mips32r2}, @samp{mips64} and @samp{mips64r2}.
 The processor names are:
 @samp{4kc}, @samp{4km}, @samp{4kp}, @samp{4ksc},
 @samp{4kec}, @samp{4kem}, @samp{4kep}, @samp{4ksd},
@@ -12065,6 +12066,10 @@ Equivalent to @samp{-march=mips32r2}.
 @opindex mips64
 Equivalent to @samp{-march=mips64}.
 
+@item -mips64r2
+@opindex mips64r2
+Equivalent to @samp{-march=mips64r2}.
+
 @item -mips16
 @itemx -mno-mips16
 @opindex mips16

gcc/testsuite/ChangeLog

+2008-07-31  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* gcc.target/mips/ext-1.c: New test.
+
 2008-07-31  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gnat.dg/discr10.ad[sb]: New test.

gcc/testsuite/gcc.target/mips/ext-1.c

+/* { dg-do compile } */
+/* { dg-mips-options "-O -mips64r2" } */
+/* { dg-final { scan-assembler "\tdext\t" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+struct
+{
+  unsigned long long a:9;
+  unsigned long long d:35;
+  unsigned long long e:10;
+  unsigned long long f:10;
+} t;
+
+NOMIPS16 unsigned long long
+f (void)
+{
+   return t.d;
+}