vect-movi.c: Check for vectorization for 64-bit and 128-bit.

2015-01-14  Tejas Belagod  <tejas.belagod@arm.com>

        * gcc.target/aarch64/vect-movi.c: Check for vectorization for 
        64-bit and 128-bit.

From-SVN: r219585

gcc/testsuite/ChangeLog

+2015-01-14  Tejas Belagod  <tejas.belagod@arm.com>
+
+	* gcc.target/aarch64/vect-movi.c: Check for vectorization for
+	64-bit and 128-bit.
+
 2015-01-14  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	PR target/64460

gcc/testsuite/gcc.target/aarch64/vect-movi.c

@@ -10,7 +10,7 @@ movi_msl8 (int *__restrict a)
 {
   int i;
 
-  /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */
+  /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.\[42\]s, 0xab, msl 8" } } */
   for (i = 0; i < N; i++)
     a[i] = 0xabff;
 }
@@ -20,7 +20,7 @@ movi_msl16 (int *__restrict a)
 {
   int i;
 
-  /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */
+  /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.\[42\]s, 0xab, msl 16" } } */
   for (i = 0; i < N; i++)
     a[i] = 0xabffff;
 }
@@ -30,7 +30,7 @@ mvni_msl8 (int *__restrict a)
 {
   int i;
 
-  /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */
+  /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.\[42\]s, 0xab, msl 8" } } */
   for (i = 0; i < N; i++)
     a[i] = 0xffff5400;
 }
@@ -40,7 +40,7 @@ mvni_msl16 (int *__restrict a)
 {
   int i;
 
-  /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */
+  /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.\[42\]s, 0xab, msl 16" } } */
   for (i = 0; i < N; i++)
     a[i] = 0xff540000;
 }