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riscv-gcc-1
Commit f29d1b66 by Richard Sandiford Committed by Richard Sandiford
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mips-protos.h (final_prescan_insn, [...]): Remove. 

	* config/mips/mips-protos.h (final_prescan_insn,
	mips_count_memory_refs, mips_fill_delay_slot): Remove.
	* config/mips/mips.h (delay_type, dslots_load_total,
	dslots_load_filled, dslots_jump_total, dslots_jump_filled,
	dslots_number_nops, num_refs, mips_load_reg, mips_load_reg2,
	mips_load_reg3, mips_load_reg4): Remove.
	(MASK_STATS): Remove.
	(MASK_EXPLICIT_RELOCS): Reuse its value.
	(TARGET_STATS): Remove.
	(TARGET_SWITCHES): Turn -mstats and -mno-stats into no-ops.
	Warn that -mstats is now ignored.
	(FINAL_PRESCAN_INSN): Undefine.
	(DBR_OUTPUT_SEQEND): Remove handling of dslot statistics.
	(ASM_OUTPUT_REG_POP): Likewise.
	* config/mips/mips.c (dslots_load_total, dslots_load_filled,
	dslots_jump_total, dslots_jump_filled, dslots_number_nops, num_refs,
	mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4,
	mips_fill_delay_slot, mips_count_memory_refs,
	final_prescan_insn): Remove.
	(output_block_move): Remove calls to mips_count_memory_refs.
	(print_operand): Remove printing of #nop for TARGET_STATS.
	(mips_output_function_epilogue): Remove TARGET_STATS code.
	Reorganize setting of fnnmae.
	* config/mips/mips.md: Remove handling of dslot statistics
	throughout file.  Change all fcmp patterns into normal asm
	templates, removing calls to mips_fill_delay_slot.
	* doc/invoke.texi: Remove documentation of -mstats.

From-SVN: r66951
parent 30a38382
Showing with 89 additions and 186 deletions
gcc/ChangeLog
2003-05-19 Richard Sandiford <rsandifo@redhat.com> 2003-05-19 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (final_prescan_insn,
mips_count_memory_refs, mips_fill_delay_slot): Remove.
* config/mips/mips.h (delay_type, dslots_load_total,
dslots_load_filled, dslots_jump_total, dslots_jump_filled,
dslots_number_nops, num_refs, mips_load_reg, mips_load_reg2,
mips_load_reg3, mips_load_reg4): Remove.
(MASK_STATS): Remove.
(MASK_EXPLICIT_RELOCS): Reuse its value.
(TARGET_STATS): Remove.
(TARGET_SWITCHES): Turn -mstats and -mno-stats into no-ops.
Warn that -mstats is now ignored.
(FINAL_PRESCAN_INSN): Undefine.
(DBR_OUTPUT_SEQEND): Remove handling of dslot statistics.
(ASM_OUTPUT_REG_POP): Likewise.
* config/mips/mips.c (dslots_load_total, dslots_load_filled,
dslots_jump_total, dslots_jump_filled, dslots_number_nops, num_refs,
mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4,
mips_fill_delay_slot, mips_count_memory_refs,
final_prescan_insn): Remove.
(output_block_move): Remove calls to mips_count_memory_refs.
(print_operand): Remove printing of #nop for TARGET_STATS.
(mips_output_function_epilogue): Remove TARGET_STATS code.
Reorganize setting of fnnmae.
* config/mips/mips.md: Remove handling of dslot statistics
throughout file. Change all fcmp patterns into normal asm
templates, removing calls to mips_fill_delay_slot.
* doc/invoke.texi: Remove documentation of -mstats.
2003-05-19 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (mips_class_max_nregs): Return the number of * config/mips/mips.c (mips_class_max_nregs): Return the number of
words in the mode. words in the mode.
......
gcc/config/mips/mips-protos.h
...@@ -87,18 +87,13 @@ extern bool mips_expand_unaligned_load PARAMS ((rtx, rtx, ...@@ -87,18 +87,13 @@ extern bool mips_expand_unaligned_load PARAMS ((rtx, rtx,
extern bool mips_expand_unaligned_store PARAMS ((rtx, rtx, extern bool mips_expand_unaligned_store PARAMS ((rtx, rtx,
unsigned int, unsigned int,
int)); int));
extern void final_prescan_insn PARAMS ((rtx, rtx *, int));
extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *, extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *,
tree, rtx)); tree, rtx));
extern void gen_conditional_move PARAMS ((rtx *)); extern void gen_conditional_move PARAMS ((rtx *));
extern void mips_gen_conditional_trap PARAMS ((rtx *)); extern void mips_gen_conditional_trap PARAMS ((rtx *));
extern void mips_emit_fcc_reload PARAMS ((rtx, rtx, rtx)); extern void mips_emit_fcc_reload PARAMS ((rtx, rtx, rtx));
extern void mips_set_return_address PARAMS ((rtx, rtx)); extern void mips_set_return_address PARAMS ((rtx, rtx));
extern void mips_count_memory_refs PARAMS ((rtx, int));
extern HOST_WIDE_INT mips_debugger_offset PARAMS ((rtx, HOST_WIDE_INT)); extern HOST_WIDE_INT mips_debugger_offset PARAMS ((rtx, HOST_WIDE_INT));
extern const char *mips_fill_delay_slot PARAMS ((const char *,
enum delay_type, rtx *,
rtx));
extern rtx mips_subword PARAMS ((rtx, int)); extern rtx mips_subword PARAMS ((rtx, int));
extern bool mips_split_64bit_move_p PARAMS ((rtx, rtx)); extern bool mips_split_64bit_move_p PARAMS ((rtx, rtx));
extern void mips_split_64bit_move PARAMS ((rtx, rtx)); extern void mips_split_64bit_move PARAMS ((rtx, rtx));
......
gcc/config/mips/mips.h
...@@ -43,14 +43,6 @@ enum cmp_type { ...@@ -43,14 +43,6 @@ enum cmp_type {
CMP_MAX /* max comparison type */ CMP_MAX /* max comparison type */
}; };
/* types of delay slot */
enum delay_type {
DELAY_NONE, /* no delay slot */
DELAY_LOAD, /* load from memory delay */
DELAY_HILO, /* move from/to hi/lo registers */
DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
};
/* Which processor to schedule for. Since there is no difference between /* Which processor to schedule for. Since there is no difference between
a R2000 and R3000 in terms of the scheduler, we collapse them into a R2000 and R3000 in terms of the scheduler, we collapse them into
just an R3000. The elements of the enumeration must match exactly just an R3000. The elements of the enumeration must match exactly
...@@ -164,16 +156,6 @@ extern const char *mips_abi_string; /* for -mabi={32,n32,64} */ ...@@ -164,16 +156,6 @@ extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
extern const char *mips_entry_string; /* for -mentry */ extern const char *mips_entry_string; /* for -mentry */
extern const char *mips_no_mips16_string;/* for -mno-mips16 */ extern const char *mips_no_mips16_string;/* for -mno-mips16 */
extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */ extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
extern int dslots_load_total; /* total # load related delay slots */
extern int dslots_load_filled; /* # filled load delay slots */
extern int dslots_jump_total; /* total # jump related delay slots */
extern int dslots_jump_filled; /* # filled jump delay slots */
extern int dslots_number_nops; /* # of nops needed by previous insn */
extern int num_refs[3]; /* # 1/2/3 word references */
extern GTY(()) rtx mips_load_reg; /* register to check for load delay */
extern GTY(()) rtx mips_load_reg2; /* 2nd reg to check for load delay */
extern GTY(()) rtx mips_load_reg3; /* 3rd reg to check for load delay */
extern GTY(()) rtx mips_load_reg4; /* 4th reg to check for load delay */
extern int mips_string_length; /* length of strings for mips16 */ extern int mips_string_length; /* length of strings for mips16 */
extern const struct mips_cpu_info mips_cpu_info_table[]; extern const struct mips_cpu_info mips_cpu_info_table[];
extern const struct mips_cpu_info *mips_arch_info; extern const struct mips_cpu_info *mips_arch_info;
...@@ -202,7 +184,7 @@ extern void sbss_section PARAMS ((void)); ...@@ -202,7 +184,7 @@ extern void sbss_section PARAMS ((void));
#define MASK_GPOPT 0x00000008 /* Optimize for global pointer */ #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
#define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */ #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
#define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */ #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
#define MASK_STATS 0x00000040 /* print statistics to stderr */ #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
#define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/ #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
#define MASK_SOFT_FLOAT 0x00000100 /* software floating point */ #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
#define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */ #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
...@@ -228,7 +210,6 @@ extern void sbss_section PARAMS ((void)); ...@@ -228,7 +210,6 @@ extern void sbss_section PARAMS ((void));
multiply-add operations. */ multiply-add operations. */
#define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely #define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
instructions. */ instructions. */
#define MASK_EXPLICIT_RELOCS 0x04000000 /* Use relocation operators. */
/* Debug switches, not documented */ /* Debug switches, not documented */
#define MASK_DEBUG 0 /* unused */ #define MASK_DEBUG 0 /* unused */
...@@ -274,9 +255,6 @@ extern void sbss_section PARAMS ((void)); ...@@ -274,9 +255,6 @@ extern void sbss_section PARAMS ((void));
/* Optimize for Sdata/Sbss */ /* Optimize for Sdata/Sbss */
#define TARGET_GP_OPT (target_flags & MASK_GPOPT) #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
/* print program statistics */
#define TARGET_STATS (target_flags & MASK_STATS)
/* call memcpy instead of inline code */ /* call memcpy instead of inline code */
#define TARGET_MEMCPY (target_flags & MASK_MEMCPY) #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
...@@ -590,9 +568,9 @@ extern void sbss_section PARAMS ((void)); ...@@ -590,9 +568,9 @@ extern void sbss_section PARAMS ((void));
N_("Don't use GP relative sdata/sbss sections")}, \ N_("Don't use GP relative sdata/sbss sections")}, \
{"no-gpopt", -MASK_GPOPT, \ {"no-gpopt", -MASK_GPOPT, \
N_("Don't use GP relative sdata/sbss sections")}, \ N_("Don't use GP relative sdata/sbss sections")}, \
{"stats", MASK_STATS, \ {"stats", 0, \
N_("Output compiler statistics")}, \ N_("Output compiler statistics (now ignored)")}, \
{"no-stats", -MASK_STATS, \ {"no-stats", 0, \
N_("Don't output compiler statistics")}, \ N_("Don't output compiler statistics")}, \
{"memcpy", MASK_MEMCPY, \ {"memcpy", MASK_MEMCPY, \
N_("Don't optimize block moves")}, \ N_("Don't optimize block moves")}, \
...@@ -3403,26 +3381,6 @@ typedef struct mips_args { ...@@ -3403,26 +3381,6 @@ typedef struct mips_args {
#define SPECIAL_MODE_PREDICATES \ #define SPECIAL_MODE_PREDICATES \
"pc_or_label_operand", "pc_or_label_operand",
/* If defined, a C statement to be executed just prior to the
output of assembler code for INSN, to modify the extracted
operands so they will be output differently.
Here the argument OPVEC is the vector containing the operands
extracted from INSN, and NOPERANDS is the number of elements of
the vector which contain meaningful data for this insn. The
contents of this vector are what will be used to convert the
insn template into assembler code, so you can change the
assembler output by changing the contents of the vector.
We use it to check if the current insn needs a nop in front of it
because of load delays, and also to update the delay slot
statistics. */
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
final_prescan_insn (INSN, OPVEC, NOPERANDS)
/* Control the assembler format that we output. */ /* Control the assembler format that we output. */
...@@ -3816,7 +3774,6 @@ do \ ...@@ -3816,7 +3774,6 @@ do \
if (set_noreorder > 0 && --set_noreorder == 0) \ if (set_noreorder > 0 && --set_noreorder == 0) \
fputs ("\t.set\treorder\n", STREAM); \ fputs ("\t.set\treorder\n", STREAM); \
\ \
dslots_jump_filled++; \
fputs ("\n", STREAM); \ fputs ("\n", STREAM); \
} \ } \
while (0) while (0)
...@@ -4107,8 +4064,6 @@ do \ ...@@ -4107,8 +4064,6 @@ do \
if (! set_noreorder) \ if (! set_noreorder) \
fprintf (STREAM, "\t.set\tnoreorder\n"); \ fprintf (STREAM, "\t.set\tnoreorder\n"); \
\ \
dslots_load_total++; \
dslots_load_filled++; \
fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
TARGET_64BIT ? "ld" : "lw", \ TARGET_64BIT ? "ld" : "lw", \
reg_names[REGNO], \ reg_names[REGNO], \
......
gcc/config/mips/mips.md
...@@ -3444,8 +3444,6 @@ ...@@ -3444,8 +3444,6 @@
"!TARGET_MIPS16" "!TARGET_MIPS16"
"* "*
{ {
dslots_jump_total++;
dslots_jump_filled++;
operands[2] = const0_rtx; operands[2] = const0_rtx;
if (REGNO (operands[0]) == REGNO (operands[1])) if (REGNO (operands[0]) == REGNO (operands[1]))
...@@ -3469,8 +3467,6 @@ ...@@ -3469,8 +3467,6 @@
"* "*
{ {
unsigned int regno1; unsigned int regno1;
dslots_jump_total++;
dslots_jump_filled++;
operands[2] = const0_rtx; operands[2] = const0_rtx;
if (GET_CODE (operands[1]) == REG) if (GET_CODE (operands[1]) == REG)
...@@ -3520,8 +3516,6 @@ ...@@ -3520,8 +3516,6 @@
"!TARGET_MIPS16" "!TARGET_MIPS16"
"* "*
{ {
dslots_jump_total += 2;
dslots_jump_filled += 2;
operands[4] = const0_rtx; operands[4] = const0_rtx;
if (optimize && find_reg_note (insn, REG_DEAD, operands[1])) if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
...@@ -3556,8 +3550,6 @@ move\\t%0,%z4\\n\\ ...@@ -3556,8 +3550,6 @@ move\\t%0,%z4\\n\\
"TARGET_64BIT && !TARGET_MIPS16" "TARGET_64BIT && !TARGET_MIPS16"
"* "*
{ {
dslots_jump_total += 2;
dslots_jump_filled += 2;
operands[4] = const0_rtx; operands[4] = const0_rtx;
if (optimize && find_reg_note (insn, REG_DEAD, operands[1])) if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
...@@ -6560,8 +6552,6 @@ move\\t%0,%z4\\n\\ ...@@ -6560,8 +6552,6 @@ move\\t%0,%z4\\n\\
"* "*
{ {
operands[4] = const0_rtx; operands[4] = const0_rtx;
dslots_jump_total += 3;
dslots_jump_filled += 2;
return \"sll\\t%3,%2,26\\n\\ return \"sll\\t%3,%2,26\\n\\
\\tbgez\\t%3,1f\\n\\ \\tbgez\\t%3,1f\\n\\
...@@ -6917,8 +6907,6 @@ move\\t%0,%z4\\n\\ ...@@ -6917,8 +6907,6 @@ move\\t%0,%z4\\n\\
"* "*
{ {
operands[4] = const0_rtx; operands[4] = const0_rtx;
dslots_jump_total += 3;
dslots_jump_filled += 2;
return \"sll\\t%3,%2,26\\n\\ return \"sll\\t%3,%2,26\\n\\
\\tbgez\\t%3,1f\\n\\ \\tbgez\\t%3,1f\\n\\
...@@ -7297,8 +7285,6 @@ move\\t%0,%z4\\n\\ ...@@ -7297,8 +7285,6 @@ move\\t%0,%z4\\n\\
"* "*
{ {
operands[4] = const0_rtx; operands[4] = const0_rtx;
dslots_jump_total += 3;
dslots_jump_filled += 2;
return \"sll\\t%3,%2,26\\n\\ return \"sll\\t%3,%2,26\\n\\
\\tbgez\\t%3,1f\\n\\ \\tbgez\\t%3,1f\\n\\
...@@ -9145,216 +9131,162 @@ move\\t%0,%z4\\n\\ ...@@ -9145,216 +9131,162 @@ move\\t%0,%z4\\n\\
(unordered:CC (match_operand:DF 1 "register_operand" "f") (unordered:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"* "c.un.d\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.un.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunlt_df" (define_insn "sunlt_df"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(unlt:CC (match_operand:DF 1 "register_operand" "f") (unlt:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"* "c.ult.d\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.ult.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "suneq_df" (define_insn "suneq_df"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(uneq:CC (match_operand:DF 1 "register_operand" "f") (uneq:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"* "c.ueq.d\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.ueq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunle_df" (define_insn "sunle_df"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(unle:CC (match_operand:DF 1 "register_operand" "f") (unle:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"* "c.ule.d\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.ule.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "seq_df" (define_insn "seq_df"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(eq:CC (match_operand:DF 1 "register_operand" "f") (eq:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"* "c.eq.d\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "slt_df" (define_insn "slt_df"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(lt:CC (match_operand:DF 1 "register_operand" "f") (lt:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"* "c.lt.d\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sle_df" (define_insn "sle_df"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(le:CC (match_operand:DF 1 "register_operand" "f") (le:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"* "c.le.d\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sgt_df" (define_insn "sgt_df"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(gt:CC (match_operand:DF 1 "register_operand" "f") (gt:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"* "c.lt.d\t%Z0%2,%1"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sge_df" (define_insn "sge_df"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(ge:CC (match_operand:DF 1 "register_operand" "f") (ge:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))] (match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"* "c.le.d\t%Z0%2,%1"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunordered_sf" (define_insn "sunordered_sf"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(unordered:CC (match_operand:SF 1 "register_operand" "f") (unordered:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"* "c.un.s\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.un.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunlt_sf" (define_insn "sunlt_sf"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(unlt:CC (match_operand:SF 1 "register_operand" "f") (unlt:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"* "c.ult.s\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.ult.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "suneq_sf" (define_insn "suneq_sf"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(uneq:CC (match_operand:SF 1 "register_operand" "f") (uneq:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"* "c.ueq.s\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.ueq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunle_sf" (define_insn "sunle_sf"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(unle:CC (match_operand:SF 1 "register_operand" "f") (unle:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"* "c.ule.s\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.ule.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "seq_sf" (define_insn "seq_sf"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(eq:CC (match_operand:SF 1 "register_operand" "f") (eq:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"* "c.eq.s\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "slt_sf" (define_insn "slt_sf"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(lt:CC (match_operand:SF 1 "register_operand" "f") (lt:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"* "c.lt.s\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sle_sf" (define_insn "sle_sf"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(le:CC (match_operand:SF 1 "register_operand" "f") (le:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"* "c.le.s\t%Z0%1,%2"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sgt_sf" (define_insn "sgt_sf"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(gt:CC (match_operand:SF 1 "register_operand" "f") (gt:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"* "c.lt.s\t%Z0%2,%1"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sge_sf" (define_insn "sge_sf"
[(set (match_operand:CC 0 "register_operand" "=z") [(set (match_operand:CC 0 "register_operand" "=z")
(ge:CC (match_operand:SF 1 "register_operand" "f") (ge:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))] (match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"* "c.le.s\t%Z0%2,%1"
{ [(set_attr "type" "fcmp")
return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); (set_attr "mode" "FPSW")])
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
;; ;;
......
gcc/doc/invoke.texi
...@@ -472,7 +472,7 @@ in the following sections. ...@@ -472,7 +472,7 @@ in the following sections.
-mno-memcpy -mno-mips-tfile -mno-rnames -mno-stats @gol -mno-memcpy -mno-mips-tfile -mno-rnames -mno-stats @gol
-mrnames -msoft-float @gol -mrnames -msoft-float @gol
-m4650 -msingle-float -mmad @gol -m4650 -msingle-float -mmad @gol
-mstats -EL -EB -G @var{num} -nocpp @gol -EL -EB -G @var{num} -nocpp @gol
-mabi=32 -mabi=n32 -mabi=64 -mabi=eabi -mabi-fake-default @gol -mabi=32 -mabi=n32 -mabi=64 -mabi=eabi -mabi-fake-default @gol
-mfix7000 -mno-crt0 -mflush-func=@var{func} -mno-flush-func @gol -mfix7000 -mno-crt0 -mflush-func=@var{func} -mno-flush-func @gol
-mbranch-likely -mno-branch-likely} -mbranch-likely -mno-branch-likely}
...@@ -7863,15 +7863,6 @@ assembler to generate one word memory references instead of using two ...@@ -7863,15 +7863,6 @@ assembler to generate one word memory references instead of using two
words for short global or static data items. This is on by default if words for short global or static data items. This is on by default if
optimization is selected. optimization is selected.
@item -mstats
@itemx -mno-stats
@opindex mstats
@opindex mno-stats
For each non-inline function processed, the @option{-mstats} switch
causes the compiler to emit one line to the standard error file to
print statistics about the program (number of registers saved, stack
size, etc.).
@item -mmemcpy @item -mmemcpy
@itemx -mno-memcpy @itemx -mno-memcpy
@opindex mmemcpy @opindex mmemcpy
......
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