Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
f2974b07
Commit
f2974b07
authored
Aug 12, 1994
by
Richard Kenner
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
(movsf): Don't truncate if not register; clean up.
From-SVN: r7907
parent
1d12df72
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
11 additions
and
11 deletions
+11
-11
gcc/config/rs6000/rs6000.md
+11
-11
No files found.
gcc/config/rs6000/rs6000.md
View file @
f2974b07
...
@@ -3794,18 +3794,18 @@
...
@@ -3794,18 +3794,18 @@
if (GET_CODE (operands
[
0
]
) == MEM)
if (GET_CODE (operands
[
0
]
) == MEM)
{
{
operands
[
1
]
= force_reg (SFmode, operands
[
1
]
);
/
*
If operands
[
1
]
is a register, it may have double-precision data
if (! TARGET_POWERPC)
in it, so truncate it to single precision. We need not do
if (reload_in_progress || reload_completed)
this for POWERPC.
*
/
emit_insn (gen_truncdfsf2 (operands
[
1
]
,
if (! TARGET_POWERPC && GET_CODE (operands
[
1
]
) == REG)
{
rtx newreg = reload_in_progress ? operands
[
1
]
: gen_reg_rtx (SFmode);
emit_insn (gen_truncdfsf2 (newreg,
gen_rtx (SUBREG, DFmode, operands
[
1
]
, 0)));
gen_rtx (SUBREG, DFmode, operands
[
1
]
, 0)));
else
operands
[
1
]
= newreg;
{
}
rtx newreg = gen_reg_rtx (SFmode);
emit_insn (gen_truncdfsf2 (newreg,
operands[1] = force_reg (SFmode, operands[1]);
gen_rtx (SUBREG, DFmode, operands
[
1
]
, 0)));
operands
[
1
]
= newreg;
}
}
}
if (GET_CODE (operands
[
0
]
) == REG && REGNO (operands
[
0
]
) < 32)
if (GET_CODE (operands
[
0
]
) == REG && REGNO (operands
[
0
]
) < 32)
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment