rs6000-c.c: Add support for builtins vector unsigned int vec_parity_lsbb (vector signed int)...

gcc/ChangeLog:

2017-07-11  Carl Love  <cel@us.ibm.com>

	* config/rs6000/rs6000-c.c: Add support for builtins
	vector unsigned int vec_parity_lsbb (vector signed int);
	vector unsigned int vec_parity_lsbb (vector unsigned int);
	vector unsigned __int128 vec_parity_lsbb (vector signed __int128);
	vector unsigned __int128 vec_parity_lsbb (vector unsigned __int128);
	vector unsigned long long vec_parity_lsbb (vector signed long long);
	vector unsigned long long vec_parity_lsbb (vector unsigned long long);
	* config/rs6000/rs6000-builtin.def (VPARITY_LSBB): Add BU_P9V_OVERLOAD1.
	* config/rs6000/altivec.h (vec_parity_lsbb): Add define.
	* doc/extend.texi: Update the built-in documentation file for the
	new built-in functions.

gcc/testsuite/ChangeLog:

2017-07-11  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtins-2-p9-runnable.c: Add new file with
	test cases for the builtins.

From-SVN: r250135

gcc/ChangeLog

+2017-07-11  Carl Love  <cel@us.ibm.com>
+
+	* config/rs6000/rs6000-c.c: Add support for builtins
+	vector unsigned int vec_parity_lsbb (vector signed int);
+	vector unsigned int vec_parity_lsbb (vector unsigned int);
+	vector unsigned __int128 vec_parity_lsbb (vector signed __int128);
+	vector unsigned __int128 vec_parity_lsbb (vector unsigned __int128);
+	vector unsigned long long vec_parity_lsbb (vector signed long long);
+	vector unsigned long long vec_parity_lsbb (vector unsigned long long);
+	* config/rs6000/rs6000-builtin.def (VPARITY_LSBB): Add BU_P9V_OVERLOAD1.
+	* config/rs6000/altivec.h (vec_parity_lsbb): Add define.
+	* doc/extend.texi: Update the built-in documentation file for the
+	new built-in functions.
+
 2017-07-11  David Malcolm  <dmalcolm@redhat.com>
 
 	* diagnostic-show-locus.c: Include "gcc-rich-location.h".

gcc/config/rs6000/altivec.h

@@ -419,6 +419,7 @@
 #ifdef __POWER9_VECTOR__
 /* Vector additions added in ISA 3.0.  */
 #define vec_pack_to_short_fp32 __builtin_vec_convert_4f32_8i16
+#define vec_parity_lsbb __builtin_vec_vparity_lsbb
 #define vec_vctz __builtin_vec_vctz
 #define vec_cnttz __builtin_vec_vctz
 #define vec_vctzb __builtin_vec_vctzb

gcc/config/rs6000/rs6000-builtin.def

@@ -2287,6 +2287,7 @@ BU_P9V_OVERLOAD_1 (VPRTYB,	"vprtyb")
 BU_P9V_OVERLOAD_1 (VPRTYBD,	"vprtybd")
 BU_P9V_OVERLOAD_1 (VPRTYBQ,	"vprtybq")
 BU_P9V_OVERLOAD_1 (VPRTYBW,	"vprtybw")
+BU_P9V_OVERLOAD_1 (VPARITY_LSBB,	"vparity_lsbb")
 
 /* 2 argument functions added in ISA 3.0 (power9).  */
 BU_P9_2 (CMPRB,	"byte_in_range",	CONST,	cmprb)

gcc/config/rs6000/rs6000-c.c

@@ -5419,6 +5419,19 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
     RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
 
+  { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
+    RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
+  { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
+    RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
+  { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
+  { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
+    RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
+  { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
+    RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 },
+  { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
+    RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
+
   { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
   { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,

gcc/doc/extend.texi

@@ -18288,6 +18288,13 @@ vector unsigned char vec_insert4b (vector unsigned int, vector unsigned char,
 vector signed char vec_insert4b (long long, vector signed char, const int);
 vector unsigned char vec_insert4b (long long, vector unsigned char, const int);
 
+vector unsigned int vec_parity_lsbb (vector signed int);
+vector unsigned int vec_parity_lsbb (vector unsigned int);
+vector unsigned __int128 vec_parity_lsbb (vector signed __int128);
+vector unsigned __int128 vec_parity_lsbb (vector unsigned __int128);
+vector unsigned long long vec_parity_lsbb (vector signed long long);
+vector unsigned long long vec_parity_lsbb (vector unsigned long long);
+
 vector int vec_vprtyb (vector int);
 vector unsigned int vec_vprtyb (vector unsigned int);
 vector long long vec_vprtyb (vector long long);

gcc/testsuite/ChangeLog

+2017-07-11  Carl Love  <cel@us.ibm.com>
+
+	* gcc.target/powerpc/builtins-2-p9-runnable.c: Add new file with
+	test cases for the builtins.
+
 2017-07-11  Yury Gribov  <tetra2005@gmail.com>
 
 	* lib/profopt.exp: Print relative names in UNSUPPORTED

gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c

+/* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+
+#include <altivec.h> // vector
+
+void abort (void);
+
+int main() {
+  int i;
+  vector int vsia;
+  vector unsigned int vsir, vsiexpt;
+  vector unsigned int vuia, vuir, vuiexpt;
+  vector signed long long vslla;
+  vector unsigned long long vsllr, vsllexpt;
+  vector unsigned long long vulla, vullr, vullexpt;
+  vector __int128_t  vs128a;
+  vector __uint128_t vs128r, vs128expt;
+  vector __uint128_t vu128a, vu128r, vu128expt;  
+
+  /* Returns a vector with each element containing the parity of the low-order
+     bit of each of the bytes in that element.  Note results are always
+     returned in an unsinged type, per the ABI spec.  */
+  vsia = (vector int) {0x10101010, 0x10101011, 0x10101111, 0x10111111};
+  vsiexpt = (vector unsigned int){0x0, 0x1, 0x0, 0x1};
+
+  vuia = (vector unsigned int) {0x000010000, 0x00010001,
+				0x10100000, 0x000010101};
+  vuiexpt = (vector unsigned int){0x1, 0x0, 0x0, 0x1};
+
+  vslla = (vector long long) {0x0000000000010000,  0x0001000100010000};
+  vsllexpt = (vector unsigned long long){0x1, 0x1};
+
+  vulla = (vector unsigned long long)   {0x0000000000000001,
+					 0x0001000000000001};
+  vullexpt = (vector unsigned long long){0x1, 0x0};
+
+  vs128a = (vector __int128_t) {0x0000000000001};
+  vs128expt = (vector __uint128_t) {0x1};
+  vu128a = (vector __uint128_t) {0x1000000000001};
+  vu128expt = (vector __uint128_t) {0x0};
+
+  vsir = vec_parity_lsbb(vsia);
+  vuir = vec_parity_lsbb(vuia);
+  vsllr = vec_parity_lsbb(vslla);
+  vullr = vec_parity_lsbb(vulla);
+  vs128r = vec_parity_lsbb(vs128a);
+  vu128r = vec_parity_lsbb(vu128a);
+
+  for(i = 0; i< 4; i++) {
+    if (vsir[i] != vsiexpt[i])
+      abort();
+
+    if (vuir[i] != vuiexpt[i])
+      abort();
+  }
+
+  for(i = 0; i< 2; i++) {
+    if (vsllr[i] != vsllexpt[i])
+      abort();
+
+    if (vullr[i] != vullexpt[i])
+      abort();
+  }
+
+  if (vs128r[0] != vs128expt[0])
+    abort();
+
+  if (vu128r[0] != vu128expt[0])
+    abort();
+}