Skip to content

R
riscv-gcc-1
Commit f259abd2 by Jakub Jelinek Committed by Jakub Jelinek
Options

re PR rtl-optimization/87817 (gcc.target/i386/bmi2-bzhi-2.c execution test) 

	PR rtl-optimization/87817
	* config/i386/i386.md (bmi2_bzhi_<mode>3, *bmi2_bzhi_<mode>3,
	*bmi2_bzhi_<mode>3_1, *bmi2_bzhi_<mode>3_1_ccz): Use IF_THEN_ELSE
	in the pattern to avoid triggering UB when operands[2] is zero.
	(tbm_bextri_<mode>): New expander.  Renamed the old define_insn to ...
	(*tbm_bextri_<mode>): ... this.

From-SVN: r266340
parent 17112570
Showing with 63 additions and 23 deletions
gcc/ChangeLog
2018-11-21 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/87817
* config/i386/i386.md (bmi2_bzhi_<mode>3, *bmi2_bzhi_<mode>3,
*bmi2_bzhi_<mode>3_1, *bmi2_bzhi_<mode>3_1_ccz): Use IF_THEN_ELSE
in the pattern to avoid triggering UB when operands[2] is zero.
(tbm_bextri_<mode>): New expander. Renamed the old define_insn to ...
(*tbm_bextri_<mode>): ... this.
2018-11-21 Tom de Vries <tdevries@suse.de> 2018-11-21 Tom de Vries <tdevries@suse.de>
PR driver/79855 PR driver/79855
gcc/config/i386/i386.md
...@@ -13615,12 +13615,15 @@ ...@@ -13615,12 +13615,15 @@
(define_expand "bmi2_bzhi_<mode>3" (define_expand "bmi2_bzhi_<mode>3"
[(parallel [(parallel
[(set (match_operand:SWI48 0 "register_operand") [(set (match_operand:SWI48 0 "register_operand")
(zero_extract:SWI48 (if_then_else:SWI48
(match_operand:SWI48 1 "nonimmediate_operand") (ne:QI (and:SWI48 (match_operand:SWI48 2 "register_operand")
(umin:SWI48 (const_int 255))
(and:SWI48 (match_operand:SWI48 2 "register_operand") (const_int 0))
(const_int 255)) (zero_extract:SWI48
(match_dup 3)) (match_operand:SWI48 1 "nonimmediate_operand")
(umin:SWI48 (and:SWI48 (match_dup 2) (const_int 255))
(match_dup 3))
(const_int 0))
(const_int 0))) (const_int 0)))
(clobber (reg:CC FLAGS_REG))])] (clobber (reg:CC FLAGS_REG))])]
"TARGET_BMI2" "TARGET_BMI2"
...@@ -13628,12 +13631,15 @@ ...@@ -13628,12 +13631,15 @@
(define_insn "*bmi2_bzhi_<mode>3" (define_insn "*bmi2_bzhi_<mode>3"
[(set (match_operand:SWI48 0 "register_operand" "=r") [(set (match_operand:SWI48 0 "register_operand" "=r")
(zero_extract:SWI48 (if_then_else:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "rm") (ne:QI (and:SWI48 (match_operand:SWI48 2 "register_operand" "r")
(umin:SWI48 (const_int 255))
(and:SWI48 (match_operand:SWI48 2 "register_operand" "r") (const_int 0))
(const_int 255)) (zero_extract:SWI48
(match_operand:SWI48 3 "const_int_operand" "n")) (match_operand:SWI48 1 "nonimmediate_operand" "rm")
(umin:SWI48 (and:SWI48 (match_dup 2) (const_int 255))
(match_operand:SWI48 3 "const_int_operand" "n"))
(const_int 0))
(const_int 0))) (const_int 0)))
(clobber (reg:CC FLAGS_REG))] (clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT" "TARGET_BMI2 && INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT"
...@@ -13644,11 +13650,13 @@ ...@@ -13644,11 +13650,13 @@
(define_insn "*bmi2_bzhi_<mode>3_1" (define_insn "*bmi2_bzhi_<mode>3_1"
[(set (match_operand:SWI48 0 "register_operand" "=r") [(set (match_operand:SWI48 0 "register_operand" "=r")
(zero_extract:SWI48 (if_then_else:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "rm") (ne:QI (match_operand:QI 2 "register_operand" "r") (const_int 0))
(umin:SWI48 (zero_extract:SWI48
(zero_extend:SWI48 (match_operand:QI 2 "register_operand" "r")) (match_operand:SWI48 1 "nonimmediate_operand" "rm")
(match_operand:SWI48 3 "const_int_operand" "n")) (umin:SWI48 (zero_extend:SWI48 (match_dup 2))
(match_operand:SWI48 3 "const_int_operand" "n"))
(const_int 0))
(const_int 0))) (const_int 0)))
(clobber (reg:CC FLAGS_REG))] (clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT" "TARGET_BMI2 && INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT"
...@@ -13660,11 +13668,13 @@ ...@@ -13660,11 +13668,13 @@
(define_insn "*bmi2_bzhi_<mode>3_1_ccz" (define_insn "*bmi2_bzhi_<mode>3_1_ccz"
[(set (reg:CCZ FLAGS_REG) [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (compare:CCZ
(zero_extract:SWI48 (if_then_else:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "rm") (ne:QI (match_operand:QI 2 "register_operand" "r") (const_int 0))
(umin:SWI48 (zero_extract:SWI48
(zero_extend:SWI48 (match_operand:QI 2 "register_operand" "r")) (match_operand:SWI48 1 "nonimmediate_operand" "rm")
(match_operand:SWI48 3 "const_int_operand" "n")) (umin:SWI48 (zero_extend:SWI48 (match_dup 2))
(match_operand:SWI48 3 "const_int_operand" "n"))
(const_int 0))
(const_int 0)) (const_int 0))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SWI48 0 "=r"))] (clobber (match_scratch:SWI48 0 "=r"))]
...@@ -13697,7 +13707,28 @@ ...@@ -13697,7 +13707,28 @@
(set_attr "mode" "<MODE>")]) (set_attr "mode" "<MODE>")])
;; TBM instructions. ;; TBM instructions.
(define_insn "tbm_bextri_<mode>" (define_expand "tbm_bextri_<mode>"
[(parallel
[(set (match_operand:SWI48 0 "register_operand")
(zero_extract:SWI48
(match_operand:SWI48 1 "nonimmediate_operand")
(match_operand 2 "const_0_to_255_operand" "N")
(match_operand 3 "const_0_to_255_operand" "N")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_TBM"
{
if (operands[2] == const0_rtx
|| INTVAL (operands[3]) >= <MODE_SIZE> * BITS_PER_UNIT)
{
emit_move_insn (operands[0], const0_rtx);
DONE;
}
if (INTVAL (operands[2]) + INTVAL (operands[3])
> <MODE_SIZE> * BITS_PER_UNIT)
operands[2] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT - INTVAL (operands[3]));
})
(define_insn "*tbm_bextri_<mode>"
[(set (match_operand:SWI48 0 "register_operand" "=r") [(set (match_operand:SWI48 0 "register_operand" "=r")
(zero_extract:SWI48 (zero_extract:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "rm") (match_operand:SWI48 1 "nonimmediate_operand" "rm")
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment