[ARM][GCC][3/4x]: MVE intrinsics with quaternary operands.

This patch supports following MVE ACLE intrinsics with quaternary operands.

vmlaldavaq_p_s16, vmlaldavaq_p_s32, vmlaldavaq_p_u16, vmlaldavaq_p_u32, vmlaldavaxq_p_s16, vmlaldavaxq_p_s32, vmlaldavaxq_p_u16, vmlaldavaxq_p_u32, vmlsldavaq_p_s16, vmlsldavaq_p_s32, vmlsldavaxq_p_s16, vmlsldavaxq_p_s32, vmullbq_poly_m_p16, vmullbq_poly_m_p8, vmulltq_poly_m_p16, vmulltq_poly_m_p8, vqdmullbq_m_n_s16, vqdmullbq_m_n_s32, vqdmullbq_m_s16, vqdmullbq_m_s32, vqdmulltq_m_n_s16, vqdmulltq_m_n_s32, vqdmulltq_m_s16, vqdmulltq_m_s32, vqrshrnbq_m_n_s16, vqrshrnbq_m_n_s32, vqrshrnbq_m_n_u16, vqrshrnbq_m_n_u32, vqrshrntq_m_n_s16, vqrshrntq_m_n_s32, vqrshrntq_m_n_u16, vqrshrntq_m_n_u32, vqrshrunbq_m_n_s16, vqrshrunbq_m_n_s32, vqrshruntq_m_n_s16, vqrshruntq_m_n_s32, vqshrnbq_m_n_s16, vqshrnbq_m_n_s32, vqshrnbq_m_n_u16, vqshrnbq_m_n_u32, vqshrntq_m_n_s16, vqshrntq_m_n_s32, vqshrntq_m_n_u16, vqshrntq_m_n_u32, vqshrunbq_m_n_s16, vqshrunbq_m_n_s32, vqshruntq_m_n_s16, vqshruntq_m_n_s32, vrmlaldavhaq_p_s32, vrmlaldavhaq_p_u32, vrmlaldavhaxq_p_s32, vrmlsldavhaq_p_s32, vrmlsldavhaxq_p_s32, vrshrnbq_m_n_s16, vrshrnbq_m_n_s32, vrshrnbq_m_n_u16, vrshrnbq_m_n_u32, vrshrntq_m_n_s16, vrshrntq_m_n_s32, vrshrntq_m_n_u16, vrshrntq_m_n_u32, vshllbq_m_n_s16, vshllbq_m_n_s8, vshllbq_m_n_u16, vshllbq_m_n_u8, vshlltq_m_n_s16, vshlltq_m_n_s8, vshlltq_m_n_u16, vshlltq_m_n_u8, vshrnbq_m_n_s16, vshrnbq_m_n_s32, vshrnbq_m_n_u16, vshrnbq_m_n_u32, vshrntq_m_n_s16, vshrntq_m_n_s32, vshrntq_m_n_u16, vshrntq_m_n_u32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm-protos.h (arm_mve_immediate_check):
	* config/arm/arm.c (arm_mve_immediate_check): Define fuction to	check
	mode and interger value.
	* config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
	(vmlaldavaq_p_s16): Likewise.
	(vmlaldavaq_p_u32): Likewise.
	(vmlaldavaq_p_u16): Likewise.
	(vmlaldavaxq_p_s32): Likewise.
	(vmlaldavaxq_p_s16): Likewise.
	(vmlaldavaxq_p_u32): Likewise.
	(vmlaldavaxq_p_u16): Likewise.
	(vmlsldavaq_p_s32): Likewise.
	(vmlsldavaq_p_s16): Likewise.
	(vmlsldavaxq_p_s32): Likewise.
	(vmlsldavaxq_p_s16): Likewise.
	(vmullbq_poly_m_p8): Likewise.
	(vmullbq_poly_m_p16): Likewise.
	(vmulltq_poly_m_p8): Likewise.
	(vmulltq_poly_m_p16): Likewise.
	(vqdmullbq_m_n_s32): Likewise.
	(vqdmullbq_m_n_s16): Likewise.
	(vqdmullbq_m_s32): Likewise.
	(vqdmullbq_m_s16): Likewise.
	(vqdmulltq_m_n_s32): Likewise.
	(vqdmulltq_m_n_s16): Likewise.
	(vqdmulltq_m_s32): Likewise.
	(vqdmulltq_m_s16): Likewise.
	(vqrshrnbq_m_n_s32): Likewise.
	(vqrshrnbq_m_n_s16): Likewise.
	(vqrshrnbq_m_n_u32): Likewise.
	(vqrshrnbq_m_n_u16): Likewise.
	(vqrshrntq_m_n_s32): Likewise.
	(vqrshrntq_m_n_s16): Likewise.
	(vqrshrntq_m_n_u32): Likewise.
	(vqrshrntq_m_n_u16): Likewise.
	(vqrshrunbq_m_n_s32): Likewise.
	(vqrshrunbq_m_n_s16): Likewise.
	(vqrshruntq_m_n_s32): Likewise.
	(vqrshruntq_m_n_s16): Likewise.
	(vqshrnbq_m_n_s32): Likewise.
	(vqshrnbq_m_n_s16): Likewise.
	(vqshrnbq_m_n_u32): Likewise.
	(vqshrnbq_m_n_u16): Likewise.
	(vqshrntq_m_n_s32): Likewise.
	(vqshrntq_m_n_s16): Likewise.
	(vqshrntq_m_n_u32): Likewise.
	(vqshrntq_m_n_u16): Likewise.
	(vqshrunbq_m_n_s32): Likewise.
	(vqshrunbq_m_n_s16): Likewise.
	(vqshruntq_m_n_s32): Likewise.
	(vqshruntq_m_n_s16): Likewise.
	(vrmlaldavhaq_p_s32): Likewise.
	(vrmlaldavhaq_p_u32): Likewise.
	(vrmlaldavhaxq_p_s32): Likewise.
	(vrmlsldavhaq_p_s32): Likewise.
	(vrmlsldavhaxq_p_s32): Likewise.
	(vrshrnbq_m_n_s32): Likewise.
	(vrshrnbq_m_n_s16): Likewise.
	(vrshrnbq_m_n_u32): Likewise.
	(vrshrnbq_m_n_u16): Likewise.
	(vrshrntq_m_n_s32): Likewise.
	(vrshrntq_m_n_s16): Likewise.
	(vrshrntq_m_n_u32): Likewise.
	(vrshrntq_m_n_u16): Likewise.
	(vshllbq_m_n_s8): Likewise.
	(vshllbq_m_n_s16): Likewise.
	(vshllbq_m_n_u8): Likewise.
	(vshllbq_m_n_u16): Likewise.
	(vshlltq_m_n_s8): Likewise.
	(vshlltq_m_n_s16): Likewise.
	(vshlltq_m_n_u8): Likewise.
	(vshlltq_m_n_u16): Likewise.
	(vshrnbq_m_n_s32): Likewise.
	(vshrnbq_m_n_s16): Likewise.
	(vshrnbq_m_n_u32): Likewise.
	(vshrnbq_m_n_u16): Likewise.
	(vshrntq_m_n_s32): Likewise.
	(vshrntq_m_n_s16): Likewise.
	(vshrntq_m_n_u32): Likewise.
	(vshrntq_m_n_u16): Likewise.
	(__arm_vmlaldavaq_p_s32): Define intrinsic.
	(__arm_vmlaldavaq_p_s16): Likewise.
	(__arm_vmlaldavaq_p_u32): Likewise.
	(__arm_vmlaldavaq_p_u16): Likewise.
	(__arm_vmlaldavaxq_p_s32): Likewise.
	(__arm_vmlaldavaxq_p_s16): Likewise.
	(__arm_vmlaldavaxq_p_u32): Likewise.
	(__arm_vmlaldavaxq_p_u16): Likewise.
	(__arm_vmlsldavaq_p_s32): Likewise.
	(__arm_vmlsldavaq_p_s16): Likewise.
	(__arm_vmlsldavaxq_p_s32): Likewise.
	(__arm_vmlsldavaxq_p_s16): Likewise.
	(__arm_vmullbq_poly_m_p8): Likewise.
	(__arm_vmullbq_poly_m_p16): Likewise.
	(__arm_vmulltq_poly_m_p8): Likewise.
	(__arm_vmulltq_poly_m_p16): Likewise.
	(__arm_vqdmullbq_m_n_s32): Likewise.
	(__arm_vqdmullbq_m_n_s16): Likewise.
	(__arm_vqdmullbq_m_s32): Likewise.
	(__arm_vqdmullbq_m_s16): Likewise.
	(__arm_vqdmulltq_m_n_s32): Likewise.
	(__arm_vqdmulltq_m_n_s16): Likewise.
	(__arm_vqdmulltq_m_s32): Likewise.
	(__arm_vqdmulltq_m_s16): Likewise.
	(__arm_vqrshrnbq_m_n_s32): Likewise.
	(__arm_vqrshrnbq_m_n_s16): Likewise.
	(__arm_vqrshrnbq_m_n_u32): Likewise.
	(__arm_vqrshrnbq_m_n_u16): Likewise.
	(__arm_vqrshrntq_m_n_s32): Likewise.
	(__arm_vqrshrntq_m_n_s16): Likewise.
	(__arm_vqrshrntq_m_n_u32): Likewise.
	(__arm_vqrshrntq_m_n_u16): Likewise.
	(__arm_vqrshrunbq_m_n_s32): Likewise.
	(__arm_vqrshrunbq_m_n_s16): Likewise.
	(__arm_vqrshruntq_m_n_s32): Likewise.
	(__arm_vqrshruntq_m_n_s16): Likewise.
	(__arm_vqshrnbq_m_n_s32): Likewise.
	(__arm_vqshrnbq_m_n_s16): Likewise.
	(__arm_vqshrnbq_m_n_u32): Likewise.
	(__arm_vqshrnbq_m_n_u16): Likewise.
	(__arm_vqshrntq_m_n_s32): Likewise.
	(__arm_vqshrntq_m_n_s16): Likewise.
	(__arm_vqshrntq_m_n_u32): Likewise.
	(__arm_vqshrntq_m_n_u16): Likewise.
	(__arm_vqshrunbq_m_n_s32): Likewise.
	(__arm_vqshrunbq_m_n_s16): Likewise.
	(__arm_vqshruntq_m_n_s32): Likewise.
	(__arm_vqshruntq_m_n_s16): Likewise.
	(__arm_vrmlaldavhaq_p_s32): Likewise.
	(__arm_vrmlaldavhaq_p_u32): Likewise.
	(__arm_vrmlaldavhaxq_p_s32): Likewise.
	(__arm_vrmlsldavhaq_p_s32): Likewise.
	(__arm_vrmlsldavhaxq_p_s32): Likewise.
	(__arm_vrshrnbq_m_n_s32): Likewise.
	(__arm_vrshrnbq_m_n_s16): Likewise.
	(__arm_vrshrnbq_m_n_u32): Likewise.
	(__arm_vrshrnbq_m_n_u16): Likewise.
	(__arm_vrshrntq_m_n_s32): Likewise.
	(__arm_vrshrntq_m_n_s16): Likewise.
	(__arm_vrshrntq_m_n_u32): Likewise.
	(__arm_vrshrntq_m_n_u16): Likewise.
	(__arm_vshllbq_m_n_s8): Likewise.
	(__arm_vshllbq_m_n_s16): Likewise.
	(__arm_vshllbq_m_n_u8): Likewise.
	(__arm_vshllbq_m_n_u16): Likewise.
	(__arm_vshlltq_m_n_s8): Likewise.
	(__arm_vshlltq_m_n_s16): Likewise.
	(__arm_vshlltq_m_n_u8): Likewise.
	(__arm_vshlltq_m_n_u16): Likewise.
	(__arm_vshrnbq_m_n_s32): Likewise.
	(__arm_vshrnbq_m_n_s16): Likewise.
	(__arm_vshrnbq_m_n_u32): Likewise.
	(__arm_vshrnbq_m_n_u16): Likewise.
	(__arm_vshrntq_m_n_s32): Likewise.
	(__arm_vshrntq_m_n_s16): Likewise.
	(__arm_vshrntq_m_n_u32): Likewise.
	(__arm_vshrntq_m_n_u16): Likewise.
	(vmullbq_poly_m): Define polymorphic variant.
	(vmulltq_poly_m): Likewise.
	(vshllbq_m): Likewise.
	(vshrntq_m_n): Likewise.
	(vshrnbq_m_n): Likewise.
	(vshlltq_m_n): Likewise.
	(vshllbq_m_n): Likewise.
	(vrshrntq_m_n): Likewise.
	(vrshrnbq_m_n): Likewise.
	(vqshruntq_m_n): Likewise.
	(vqshrunbq_m_n): Likewise.
	(vqdmullbq_m_n): Likewise.
	(vqdmullbq_m): Likewise.
	(vqdmulltq_m_n): Likewise.
	(vqdmulltq_m): Likewise.
	(vqrshrnbq_m_n): Likewise.
	(vqrshrntq_m_n): Likewise.
	(vqrshrunbq_m_n): Likewise.
	(vqrshruntq_m_n): Likewise.
	(vqshrnbq_m_n): Likewise.
	(vqshrntq_m_n): Likewise.
	* config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
	builtin qualifiers.
	(QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
	(QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
	(QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
	* config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
	(VMLALDAVAXQ_P): Likewise.
	(VQRSHRNBQ_M_N): Likewise.
	(VQRSHRNTQ_M_N): Likewise.
	(VQSHRNBQ_M_N): Likewise.
	(VQSHRNTQ_M_N): Likewise.
	(VRSHRNBQ_M_N): Likewise.
	(VRSHRNTQ_M_N): Likewise.
	(VSHLLBQ_M_N): Likewise.
	(VSHLLTQ_M_N): Likewise.
	(VSHRNBQ_M_N): Likewise.
	(VSHRNTQ_M_N): Likewise.
	(mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
	(mve_vmlaldavaxq_p_<supf><mode>): Likewise.
	(mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
	(mve_vqrshrntq_m_n_<supf><mode>): Likewise.
	(mve_vqshrnbq_m_n_<supf><mode>): Likewise.
	(mve_vqshrntq_m_n_<supf><mode>): Likewise.
	(mve_vrmlaldavhaq_p_sv4si): Likewise.
	(mve_vrshrnbq_m_n_<supf><mode>): Likewise.
	(mve_vrshrntq_m_n_<supf><mode>): Likewise.
	(mve_vshllbq_m_n_<supf><mode>): Likewise.
	(mve_vshlltq_m_n_<supf><mode>): Likewise.
	(mve_vshrnbq_m_n_<supf><mode>): Likewise.
	(mve_vshrntq_m_n_<supf><mode>): Likewise.
	(mve_vmlsldavaq_p_s<mode>): Likewise.
	(mve_vmlsldavaxq_p_s<mode>): Likewise.
	(mve_vmullbq_poly_m_p<mode>): Likewise.
	(mve_vmulltq_poly_m_p<mode>): Likewise.
	(mve_vqdmullbq_m_n_s<mode>): Likewise.
	(mve_vqdmullbq_m_s<mode>): Likewise.
	(mve_vqdmulltq_m_n_s<mode>): Likewise.
	(mve_vqdmulltq_m_s<mode>): Likewise.
	(mve_vqrshrunbq_m_n_s<mode>): Likewise.
	(mve_vqrshruntq_m_n_s<mode>): Likewise.
	(mve_vqshrunbq_m_n_s<mode>): Likewise.
	(mve_vqshruntq_m_n_s<mode>): Likewise.
	(mve_vrmlaldavhaq_p_uv4si): Likewise.
	(mve_vrmlaldavhaxq_p_sv4si): Likewise.
	(mve_vrmlsldavhaq_p_sv4si): Likewise.
	(mve_vrmlsldavhaxq_p_sv4si): Likewise.

gcc/testsuite/ChangeLog:

2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>
            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise.

gcc/ChangeLog

 2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
             Mihail Ionescu  <mihail.ionescu@arm.com>
             Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
+	* config/arm/arm-protos.h (arm_mve_immediate_check): 
+	* config/arm/arm.c (arm_mve_immediate_check): Define fuction to	check
+	mode and interger value.
+	* config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
+	(vmlaldavaq_p_s16): Likewise.
+	(vmlaldavaq_p_u32): Likewise.
+	(vmlaldavaq_p_u16): Likewise.
+	(vmlaldavaxq_p_s32): Likewise.
+	(vmlaldavaxq_p_s16): Likewise.
+	(vmlaldavaxq_p_u32): Likewise.
+	(vmlaldavaxq_p_u16): Likewise.
+	(vmlsldavaq_p_s32): Likewise.
+	(vmlsldavaq_p_s16): Likewise.
+	(vmlsldavaxq_p_s32): Likewise.
+	(vmlsldavaxq_p_s16): Likewise.
+	(vmullbq_poly_m_p8): Likewise.
+	(vmullbq_poly_m_p16): Likewise.
+	(vmulltq_poly_m_p8): Likewise.
+	(vmulltq_poly_m_p16): Likewise.
+	(vqdmullbq_m_n_s32): Likewise.
+	(vqdmullbq_m_n_s16): Likewise.
+	(vqdmullbq_m_s32): Likewise.
+	(vqdmullbq_m_s16): Likewise.
+	(vqdmulltq_m_n_s32): Likewise.
+	(vqdmulltq_m_n_s16): Likewise.
+	(vqdmulltq_m_s32): Likewise.
+	(vqdmulltq_m_s16): Likewise.
+	(vqrshrnbq_m_n_s32): Likewise.
+	(vqrshrnbq_m_n_s16): Likewise.
+	(vqrshrnbq_m_n_u32): Likewise.
+	(vqrshrnbq_m_n_u16): Likewise.
+	(vqrshrntq_m_n_s32): Likewise.
+	(vqrshrntq_m_n_s16): Likewise.
+	(vqrshrntq_m_n_u32): Likewise.
+	(vqrshrntq_m_n_u16): Likewise.
+	(vqrshrunbq_m_n_s32): Likewise.
+	(vqrshrunbq_m_n_s16): Likewise.
+	(vqrshruntq_m_n_s32): Likewise.
+	(vqrshruntq_m_n_s16): Likewise.
+	(vqshrnbq_m_n_s32): Likewise.
+	(vqshrnbq_m_n_s16): Likewise.
+	(vqshrnbq_m_n_u32): Likewise.
+	(vqshrnbq_m_n_u16): Likewise.
+	(vqshrntq_m_n_s32): Likewise.
+	(vqshrntq_m_n_s16): Likewise.
+	(vqshrntq_m_n_u32): Likewise.
+	(vqshrntq_m_n_u16): Likewise.
+	(vqshrunbq_m_n_s32): Likewise.
+	(vqshrunbq_m_n_s16): Likewise.
+	(vqshruntq_m_n_s32): Likewise.
+	(vqshruntq_m_n_s16): Likewise.
+	(vrmlaldavhaq_p_s32): Likewise.
+	(vrmlaldavhaq_p_u32): Likewise.
+	(vrmlaldavhaxq_p_s32): Likewise.
+	(vrmlsldavhaq_p_s32): Likewise.
+	(vrmlsldavhaxq_p_s32): Likewise.
+	(vrshrnbq_m_n_s32): Likewise.
+	(vrshrnbq_m_n_s16): Likewise.
+	(vrshrnbq_m_n_u32): Likewise.
+	(vrshrnbq_m_n_u16): Likewise.
+	(vrshrntq_m_n_s32): Likewise.
+	(vrshrntq_m_n_s16): Likewise.
+	(vrshrntq_m_n_u32): Likewise.
+	(vrshrntq_m_n_u16): Likewise.
+	(vshllbq_m_n_s8): Likewise.
+	(vshllbq_m_n_s16): Likewise.
+	(vshllbq_m_n_u8): Likewise.
+	(vshllbq_m_n_u16): Likewise.
+	(vshlltq_m_n_s8): Likewise.
+	(vshlltq_m_n_s16): Likewise.
+	(vshlltq_m_n_u8): Likewise.
+	(vshlltq_m_n_u16): Likewise.
+	(vshrnbq_m_n_s32): Likewise.
+	(vshrnbq_m_n_s16): Likewise.
+	(vshrnbq_m_n_u32): Likewise.
+	(vshrnbq_m_n_u16): Likewise.
+	(vshrntq_m_n_s32): Likewise.
+	(vshrntq_m_n_s16): Likewise.
+	(vshrntq_m_n_u32): Likewise.
+	(vshrntq_m_n_u16): Likewise.
+	(__arm_vmlaldavaq_p_s32): Define intrinsic.
+	(__arm_vmlaldavaq_p_s16): Likewise.
+	(__arm_vmlaldavaq_p_u32): Likewise.
+	(__arm_vmlaldavaq_p_u16): Likewise.
+	(__arm_vmlaldavaxq_p_s32): Likewise.
+	(__arm_vmlaldavaxq_p_s16): Likewise.
+	(__arm_vmlaldavaxq_p_u32): Likewise.
+	(__arm_vmlaldavaxq_p_u16): Likewise.
+	(__arm_vmlsldavaq_p_s32): Likewise.
+	(__arm_vmlsldavaq_p_s16): Likewise.
+	(__arm_vmlsldavaxq_p_s32): Likewise.
+	(__arm_vmlsldavaxq_p_s16): Likewise.
+	(__arm_vmullbq_poly_m_p8): Likewise.
+	(__arm_vmullbq_poly_m_p16): Likewise.
+	(__arm_vmulltq_poly_m_p8): Likewise.
+	(__arm_vmulltq_poly_m_p16): Likewise.
+	(__arm_vqdmullbq_m_n_s32): Likewise.
+	(__arm_vqdmullbq_m_n_s16): Likewise.
+	(__arm_vqdmullbq_m_s32): Likewise.
+	(__arm_vqdmullbq_m_s16): Likewise.
+	(__arm_vqdmulltq_m_n_s32): Likewise.
+	(__arm_vqdmulltq_m_n_s16): Likewise.
+	(__arm_vqdmulltq_m_s32): Likewise.
+	(__arm_vqdmulltq_m_s16): Likewise.
+	(__arm_vqrshrnbq_m_n_s32): Likewise.
+	(__arm_vqrshrnbq_m_n_s16): Likewise.
+	(__arm_vqrshrnbq_m_n_u32): Likewise.
+	(__arm_vqrshrnbq_m_n_u16): Likewise.
+	(__arm_vqrshrntq_m_n_s32): Likewise.
+	(__arm_vqrshrntq_m_n_s16): Likewise.
+	(__arm_vqrshrntq_m_n_u32): Likewise.
+	(__arm_vqrshrntq_m_n_u16): Likewise.
+	(__arm_vqrshrunbq_m_n_s32): Likewise.
+	(__arm_vqrshrunbq_m_n_s16): Likewise.
+	(__arm_vqrshruntq_m_n_s32): Likewise.
+	(__arm_vqrshruntq_m_n_s16): Likewise.
+	(__arm_vqshrnbq_m_n_s32): Likewise.
+	(__arm_vqshrnbq_m_n_s16): Likewise.
+	(__arm_vqshrnbq_m_n_u32): Likewise.
+	(__arm_vqshrnbq_m_n_u16): Likewise.
+	(__arm_vqshrntq_m_n_s32): Likewise.
+	(__arm_vqshrntq_m_n_s16): Likewise.
+	(__arm_vqshrntq_m_n_u32): Likewise.
+	(__arm_vqshrntq_m_n_u16): Likewise.
+	(__arm_vqshrunbq_m_n_s32): Likewise.
+	(__arm_vqshrunbq_m_n_s16): Likewise.
+	(__arm_vqshruntq_m_n_s32): Likewise.
+	(__arm_vqshruntq_m_n_s16): Likewise.
+	(__arm_vrmlaldavhaq_p_s32): Likewise.
+	(__arm_vrmlaldavhaq_p_u32): Likewise.
+	(__arm_vrmlaldavhaxq_p_s32): Likewise.
+	(__arm_vrmlsldavhaq_p_s32): Likewise.
+	(__arm_vrmlsldavhaxq_p_s32): Likewise.
+	(__arm_vrshrnbq_m_n_s32): Likewise.
+	(__arm_vrshrnbq_m_n_s16): Likewise.
+	(__arm_vrshrnbq_m_n_u32): Likewise.
+	(__arm_vrshrnbq_m_n_u16): Likewise.
+	(__arm_vrshrntq_m_n_s32): Likewise.
+	(__arm_vrshrntq_m_n_s16): Likewise.
+	(__arm_vrshrntq_m_n_u32): Likewise.
+	(__arm_vrshrntq_m_n_u16): Likewise.
+	(__arm_vshllbq_m_n_s8): Likewise.
+	(__arm_vshllbq_m_n_s16): Likewise.
+	(__arm_vshllbq_m_n_u8): Likewise.
+	(__arm_vshllbq_m_n_u16): Likewise.
+	(__arm_vshlltq_m_n_s8): Likewise.
+	(__arm_vshlltq_m_n_s16): Likewise.
+	(__arm_vshlltq_m_n_u8): Likewise.
+	(__arm_vshlltq_m_n_u16): Likewise.
+	(__arm_vshrnbq_m_n_s32): Likewise.
+	(__arm_vshrnbq_m_n_s16): Likewise.
+	(__arm_vshrnbq_m_n_u32): Likewise.
+	(__arm_vshrnbq_m_n_u16): Likewise.
+	(__arm_vshrntq_m_n_s32): Likewise.
+	(__arm_vshrntq_m_n_s16): Likewise.
+	(__arm_vshrntq_m_n_u32): Likewise.
+	(__arm_vshrntq_m_n_u16): Likewise.
+	(vmullbq_poly_m): Define polymorphic variant.
+	(vmulltq_poly_m): Likewise.
+	(vshllbq_m): Likewise.
+	(vshrntq_m_n): Likewise.
+	(vshrnbq_m_n): Likewise.
+	(vshlltq_m_n): Likewise.
+	(vshllbq_m_n): Likewise.
+	(vrshrntq_m_n): Likewise.
+	(vrshrnbq_m_n): Likewise.
+	(vqshruntq_m_n): Likewise.
+	(vqshrunbq_m_n): Likewise.
+	(vqdmullbq_m_n): Likewise.
+	(vqdmullbq_m): Likewise.
+	(vqdmulltq_m_n): Likewise.
+	(vqdmulltq_m): Likewise.
+	(vqrshrnbq_m_n): Likewise.
+	(vqrshrntq_m_n): Likewise.
+	(vqrshrunbq_m_n): Likewise.
+	(vqrshruntq_m_n): Likewise.
+	(vqshrnbq_m_n): Likewise.
+	(vqshrntq_m_n): Likewise.
+	* config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
+	builtin qualifiers.
+	(QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
+	(QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
+	(QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
+	(QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
+	* config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
+	(VMLALDAVAXQ_P): Likewise.
+	(VQRSHRNBQ_M_N): Likewise.
+	(VQRSHRNTQ_M_N): Likewise.
+	(VQSHRNBQ_M_N): Likewise.
+	(VQSHRNTQ_M_N): Likewise.
+	(VRSHRNBQ_M_N): Likewise.
+	(VRSHRNTQ_M_N): Likewise.
+	(VSHLLBQ_M_N): Likewise.
+	(VSHLLTQ_M_N): Likewise.
+	(VSHRNBQ_M_N): Likewise.
+	(VSHRNTQ_M_N): Likewise.
+	(mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
+	(mve_vmlaldavaxq_p_<supf><mode>): Likewise.
+	(mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
+	(mve_vqrshrntq_m_n_<supf><mode>): Likewise.
+	(mve_vqshrnbq_m_n_<supf><mode>): Likewise.
+	(mve_vqshrntq_m_n_<supf><mode>): Likewise.
+	(mve_vrmlaldavhaq_p_sv4si): Likewise.
+	(mve_vrshrnbq_m_n_<supf><mode>): Likewise.
+	(mve_vrshrntq_m_n_<supf><mode>): Likewise.
+	(mve_vshllbq_m_n_<supf><mode>): Likewise.
+	(mve_vshlltq_m_n_<supf><mode>): Likewise.
+	(mve_vshrnbq_m_n_<supf><mode>): Likewise.
+	(mve_vshrntq_m_n_<supf><mode>): Likewise.
+	(mve_vmlsldavaq_p_s<mode>): Likewise.
+	(mve_vmlsldavaxq_p_s<mode>): Likewise.
+	(mve_vmullbq_poly_m_p<mode>): Likewise.
+	(mve_vmulltq_poly_m_p<mode>): Likewise.
+	(mve_vqdmullbq_m_n_s<mode>): Likewise.
+	(mve_vqdmullbq_m_s<mode>): Likewise.
+	(mve_vqdmulltq_m_n_s<mode>): Likewise.
+	(mve_vqdmulltq_m_s<mode>): Likewise.
+	(mve_vqrshrunbq_m_n_s<mode>): Likewise.
+	(mve_vqrshruntq_m_n_s<mode>): Likewise.
+	(mve_vqshrunbq_m_n_s<mode>): Likewise.
+	(mve_vqshruntq_m_n_s<mode>): Likewise.
+	(mve_vrmlaldavhaq_p_uv4si): Likewise.
+	(mve_vrmlaldavhaxq_p_sv4si): Likewise.
+	(mve_vrmlsldavhaq_p_sv4si): Likewise.
+	(mve_vrmlsldavhaxq_p_sv4si): Likewise.
+
+2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+            Mihail Ionescu  <mihail.ionescu@arm.com>
+            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 	
 	* config/arm/arm_mve.h (vabdq_m_s8): Define macro.
 	(vabdq_m_s32): Likewise.

gcc/config/arm/arm-protos.h

@@ -579,4 +579,5 @@ void arm_initialize_isa (sbitmap, const enum isa_feature *);
 
 const char * arm_gen_far_branch (rtx *, int, const char * , const char *);
 
+bool arm_mve_immediate_check(rtx, machine_mode, bool);
 #endif /* ! GCC_ARM_PROTOS_H */

gcc/config/arm/arm.c

@@ -32702,6 +32702,31 @@ arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
   return true;
 }
 
+/* To check op's immediate values matches the mode of the defined insn.  */
+bool
+arm_mve_immediate_check (rtx op, machine_mode mode, bool val)
+{
+  if (val)
+    {
+      if (((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 7)
+	   && (mode == E_V16QImode))
+	  || ((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 15)
+	   && (mode == E_V8HImode))
+	  || ((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 31)
+	   && (mode == E_V4SImode)))
+	return true;
+    }
+  else
+    {
+      if (((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 7)
+	   && (mode == E_V8HImode))
+	  || ((GET_CODE (op) == CONST_INT) && (INTVAL (op) <= 15)
+	   && (mode == E_V4SImode)))
+	return true;
+    }
+  return false;
+}
+
 /* Can output mi_thunk for all cases except for non-zero vcall_offset
    in Thumb1.  */
 static bool

gcc/config/arm/arm_mve_builtins.def

@@ -613,3 +613,44 @@ VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrq_m_n_s, v16qi, v8hi, v4si)
 VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshlq_m_n_s, v16qi, v8hi, v4si)
 VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrq_m_n_s, v16qi, v8hi, v4si)
 VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshlq_m_n_s, v16qi, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmulltq_poly_m_p, v16qi, v8hi)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmullbq_poly_m_p, v16qi, v8hi)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlaldavaxq_p_u, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vmlaldavaq_p_u, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrntq_m_n_u, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshrnbq_m_n_u, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlltq_m_n_u, v16qi, v8hi)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshllbq_m_n_u, v16qi, v8hi)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrntq_m_n_u, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vrshrnbq_m_n_u, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshrntq_m_n_u, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqshrnbq_m_n_u, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqrshrntq_m_n_u, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vqrshrnbq_m_n_u, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshruntq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshrunbq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqrshruntq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqrshrunbq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulltq_m_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmulltq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmullbq_m_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vqdmullbq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsldavaxq_p_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlsldavaq_p_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaldavaxq_p_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vmlaldavaq_p_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrntq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshrnbq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshlltq_m_n_s, v16qi, v8hi)
+VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vshllbq_m_n_s, v16qi, v8hi)
+VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrntq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vrshrnbq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshrntq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqshrnbq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqrshrntq_m_n_s, v8hi, v4si)
+VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vqrshrnbq_m_n_s, v8hi, v4si)
+VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_p_u, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaxq_p_s, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaq_p_s, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaxq_p_s, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaq_p_s, v4si)

gcc/testsuite/ChangeLog

@@ -2,6 +2,88 @@
             Mihail Ionescu  <mihail.ionescu@arm.com>
             Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c: Likewise.
+
+2020-03-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+            Mihail Ionescu  <mihail.ionescu@arm.com>
+            Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
+
 	* gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: New test.
 	* gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise.
 	* gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise.

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+  return vmlaldavaq_p_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavat.s16"  }  } */
+
+int64_t
+foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+  return vmlaldavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavat.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vmlaldavaq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavat.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vmlaldavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavat.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64_t
+foo (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+{
+  return vmlaldavaq_p_u16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavat.u16"  }  } */
+
+uint64_t
+foo1 (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+{
+  return vmlaldavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavat.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64_t
+foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vmlaldavaq_p_u32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavat.u32"  }  } */
+
+uint64_t
+foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vmlaldavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavat.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+  return vmlaldavaxq_p_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavaxt.s16"  }  } */
+
+int64_t
+foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+  return vmlaldavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavaxt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vmlaldavaxq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavaxt.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vmlaldavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavaxt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64_t
+foo (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+{
+  return vmlaldavaxq_p_u16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavaxt.u16"  }  } */
+
+uint64_t
+foo1 (uint64_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p)
+{
+  return vmlaldavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavaxt.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64_t
+foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vmlaldavaxq_p_u32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavaxt.u32"  }  } */
+
+uint64_t
+foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vmlaldavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlaldavaxt.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+  return vmlsldavaq_p_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavat.s16"  }  } */
+
+int64_t
+foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+  return vmlsldavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavat.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vmlsldavaq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavat.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vmlsldavaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavat.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+  return vmlsldavaxq_p_s16 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavaxt.s16"  }  } */
+
+int64_t
+foo1 (int64_t a, int16x8_t b, int16x8_t c, mve_pred16_t p)
+{
+  return vmlsldavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavaxt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vmlsldavaxq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavaxt.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vmlsldavaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vmlsldavaxt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vmullbq_poly_m_p16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.p16"  }  } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vmullbq_poly_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.p16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+  return vmullbq_poly_m_p8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.p8"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+  return vmullbq_poly_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmullbt.p8"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vmulltq_poly_m_p16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.p16"  }  } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vmulltq_poly_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.p16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+  return vmulltq_poly_m_p8 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.p8"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+  return vmulltq_poly_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vmulltt.p8"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+  return vqdmullbq_m_n_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+  return vqdmullbq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64x2_t
+foo (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+  return vqdmullbq_m_n_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */
+
+int64x2_t
+foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+  return vqdmullbq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqdmullbq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqdmullbq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmullbt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64x2_t
+foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqdmullbq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */
+
+int64x2_t
+foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqdmullbq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmullbt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+  return vqdmulltq_m_n_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int16x8_t a, int16_t b, mve_pred16_t p)
+{
+  return vqdmulltq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64x2_t
+foo (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+  return vqdmulltq_m_n_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */
+
+int64x2_t
+foo1 (int64x2_t inactive, int32x4_t a, int32_t b, mve_pred16_t p)
+{
+  return vqdmulltq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqdmulltq_m_s16 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqdmulltq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulltt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64x2_t
+foo (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqdmulltq_m_s32 (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */
+
+int64x2_t
+foo1 (int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqdmulltq_m (inactive, a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqdmulltt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqrshrnbq_m_n_s16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrnbt.s16"  }  } */
+
+int8x16_t
+foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqrshrnbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrnbt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqrshrnbq_m_n_s32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrnbt.s32"  }  } */
+
+int16x8_t
+foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqrshrnbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrnbt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vqrshrnbq_m_n_u16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrnbt.u16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vqrshrnbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrnbt.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vqrshrnbq_m_n_u32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrnbt.u32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vqrshrnbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrnbt.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqrshrntq_m_n_s16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrntt.s16"  }  } */
+
+int8x16_t
+foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqrshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrntt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqrshrntq_m_n_s32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrntt.s32"  }  } */
+
+int16x8_t
+foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqrshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrntt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vqrshrntq_m_n_u16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrntt.u16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vqrshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrntt.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vqrshrntq_m_n_u32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrntt.u32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vqrshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrntt.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqrshrunbq_m_n_s16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrunbt.s16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqrshrunbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrunbt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqrshrunbq_m_n_s32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrunbt.s32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqrshrunbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshrunbt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqrshruntq_m_n_s16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshruntt.s16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqrshruntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshruntt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqrshruntq_m_n_s32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshruntt.s32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqrshruntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqrshruntt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqshrnbq_m_n_s16 (a, b, 7, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrnbt.s16"  }  } */
+
+int8x16_t
+foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqshrnbq_m (a, b, 7, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrnbt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqshrnbq_m_n_s32 (a, b, 11, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrnbt.s32"  }  } */
+
+int16x8_t
+foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqshrnbq_m (a, b, 11, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrnbt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vqshrnbq_m_n_u16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrnbt.u16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vqshrnbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrnbt.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vqshrnbq_m_n_u32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrnbt.u32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vqshrnbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrnbt.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqshrntq_m_n_s16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrntt.s16"  }  } */
+
+int8x16_t
+foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrntt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqshrntq_m_n_s32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrntt.s32"  }  } */
+
+int16x8_t
+foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrntt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vqshrntq_m_n_u16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrntt.u16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vqshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrntt.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vqshrntq_m_n_u32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrntt.u32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vqshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrntt.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqshrunbq_m_n_s16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrunbt.s16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqshrunbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrunbt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqshrunbq_m_n_s32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrunbt.s32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqshrunbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshrunbt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqshruntq_m_n_s16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshruntt.s16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vqshruntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshruntt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqshruntq_m_n_s32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshruntt.s32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vqshruntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vqshruntt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vrmlaldavhaq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vrmlaldavhat.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vrmlaldavhaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vrmlaldavhat.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint64_t
+foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vrmlaldavhaq_p_u32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vrmlaldavhat.u32"  }  } */
+
+uint64_t
+foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vrmlaldavhaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vrmlaldavhat.u32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vrmlaldavhaxq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vrmlaldavhaxt.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vrmlaldavhaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vrmlaldavhaxt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vrmlsldavhaq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vrmlsldavhat.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vrmlsldavhaq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vrmlsldavhat.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int64_t
+foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vrmlsldavhaxq_p_s32 (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vrmlsldavhaxt.s32"  }  } */
+
+int64_t
+foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
+{
+  return vrmlsldavhaxq_p (a, b, c, p);
+}
+
+/* { dg-final { scan-assembler "vrmlsldavhaxt.s32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vrshrnbq_m_n_s16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */
+
+int8x16_t
+foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vrshrnbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vrshrnbq_m_n_s32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */
+
+int16x8_t
+foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vrshrnbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vrshrnbq_m_n_u16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vrshrnbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrnbt.i16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vrshrnbq_m_n_u32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vrshrnbq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrnbt.i32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vrshrntq_m_n_s16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */
+
+int8x16_t
+foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vrshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vrshrntq_m_n_s32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */
+
+int16x8_t
+foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vrshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vrshrntq_m_n_u16 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vrshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrntt.i16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vrshrntq_m_n_u32 (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vrshrntq_m (a, b, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vrshrntt.i32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
+{
+  return vshllbq_m_n_s16 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshllbt.s16"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
+{
+  return vshllbq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshllbt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
+{
+  return vshllbq_m_n_s8 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshllbt.s8"  }  } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
+{
+  return vshllbq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshllbt.s8"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vshllbq_m_n_u16 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshllbt.u16"  }  } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vshllbq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshllbt.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vshllbq_m_n_u8 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshllbt.u8"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vshllbq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshllbt.u8"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
+{
+  return vshlltq_m_n_s16 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshlltt.s16"  }  } */
+
+int32x4_t
+foo1 (int32x4_t inactive, int16x8_t a, mve_pred16_t p)
+{
+  return vshlltq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshlltt.s16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
+{
+  return vshlltq_m_n_s8 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshlltt.s8"  }  } */
+
+int16x8_t
+foo1 (int16x8_t inactive, int8x16_t a, mve_pred16_t p)
+{
+  return vshlltq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshlltt.s8"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vshlltq_m_n_u16 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshlltt.u16"  }  } */
+
+uint32x4_t
+foo1 (uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
+{
+  return vshlltq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshlltt.u16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vshlltq_m_n_u8 (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshlltt.u8"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
+{
+  return vshlltq_m (inactive, a, 1, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshlltt.u8"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vshrnbq_m_n_s16 (a, b, 8, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */
+
+int8x16_t
+foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vshrnbq_m (a, b, 8, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vshrnbq_m_n_s32 (a, b, 16, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */
+
+int16x8_t
+foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vshrnbq_m (a, b, 16, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vshrnbq_m_n_u16 (a, b, 8, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vshrnbq_m (a, b, 8, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrnbt.i16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vshrnbq_m_n_u32 (a, b, 16, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vshrnbq_m (a, b, 16, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrnbt.i32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vshrntq_m_n_s16 (a, b, 8, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrntt.i16"  }  } */
+
+int8x16_t
+foo1 (int8x16_t a, int16x8_t b, mve_pred16_t p)
+{
+  return vshrntq_m (a, b, 8, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrntt.i16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vshrntq_m_n_s32 (a, b, 16, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrntt.i32"  }  } */
+
+int16x8_t
+foo1 (int16x8_t a, int32x4_t b, mve_pred16_t p)
+{
+  return vshrntq_m (a, b, 16, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrntt.i32"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c

+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vshrntq_m_n_u16 (a, b, 8, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrntt.i16"  }  } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint16x8_t b, mve_pred16_t p)
+{
+  return vshrntq_m (a, b, 8, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrntt.i16"  }  } */

gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c

+/* { dg-do compile  } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2"  }  */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vshrntq_m_n_u32 (a, b, 16, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrntt.i32"  }  } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint32x4_t b, mve_pred16_t p)
+{
+  return vshrntq_m (a, b, 16, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vshrntt.i32"  }  } */